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| 型號： | AD7812YRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | +2.7 V to +5.5 V, 350 kSPS, 10-Bit 4-/8-Channel Sampling ADCs |
| 中文描述： | 8-CH 10-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO20 |
| 封裝： | TSSOP-20 |
| 文件頁數(shù)： | 17/19頁 |
| 文件大?。?/td> | 210K |
| 代理商： | AD7812YRU |
AD7811/AD7812
–17–
REV. B
It is possible to implement a serial interface using the data ports
on the 8051. This would also allow a full duplex serial transfer
to be implemented. The technique involves “bit banging” an
I/O port (e.g., P1.0) to generate a serial clock and using two
other I/O ports (e.g., P1.1 and P1.2) to shift data in and out—
see Figure 22.
AD7811/AD7812
*
DOUT
DIN
SCLK
RFS
TFS
8051
*
P1.0
P1.1
P1.2
P1.3
*
ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. Interfacing to the 8051 Using I/O Ports
AD7811/AD7812 to TMS320C5x
The serial interface on the TMS320C5x uses a continuous
serial clock and frame synchronization signals to synchronize
the data transfer operations with peripheral devices like the
AD7811. Frame synchronization inputs have been supplied on
the AD7811/AD7812 to allow easy interfacing with no extra
gluing logic. The serial port of the TMS320C5x is set up to
operate in Burst Mode with internal CLKX (Tx serial clock)
and FSX (Tx frame sync). The Serial Port Control register
(SPC) must have the following setup: F0 = 0, FSM = 1,
MCM = 1 and TXM = 1. The connection diagram is shown
in Figure 23.
AD7811/AD7812
*
DOUT
SCLK
RFS
TFS
TMS320C5x
*
CLKX
CLKR
FSX
*
ADDITIONAL PINS OMITTED FOR CLARITY
FSR
DR
DIN
DT
Figure 23. Interfacing to the TMS320C5x
AD7811/AD7812 to ADSP-21xx
The ADSP-21xx family of DSPs are easily interfaced to the
AD7811/AD7812 without the need for extra gluing logic. The
SPORT is operated in normal framing mode. The SPORT
control register should be set up as follows:
TFSW
= RFSW = 0, Normal Framing
INVRFS = INVTFS = 0, Active High Frame Signal
DTYPE = 00, Right Justify Data
SLEN
= 1001, 10-Bit Data Words
ISCLK
= 1, Internal Serial Clock
TFSR
= RFSR = 1, Frame Every Word
IRFS
= 0, External Framing Signal
ITFS
= 1, Internal Framing Signal
The 10-bit data words will be right justified in the 16-bit serial
data registers when using this configuration. Figure 24 shows
the connection diagram.
AD7811/AD7812
*
DOUT
DIN
SCLK
RFS
TFS
ADSP-21xx
*
SCLK
DR
DT
RFS
*
ADDITIONAL PINS OMITTED FOR CLARITY
TFS
Figure 24. Interfacing to the ADSP-21xx
AD7811/AD7812 to DSP56xxx
The connection diagram in Figure 25 shows how the AD7811
and AD7812 can be connected to the SSI (Synchronous Serial
Interface) of the DSP56xxx family of DSPs from Motorola. The
SSI is operated in Synchronous Mode (SYN bit in CRB =1)
with internally generated 1-bit clock period frame sync for both
Tx and Rx (FSL1 and FSL0 bits in CRB = 1 and 0 respectively).
AD7811/AD7812
*
DOUT
SCLK
DSP56xxx
*
SCK
SRD
*
ADDITIONAL PINS OMITTED FOR CLARITY
DIN
STD
SC2
RFS
TFS
Figure 25. Interfacing to the DSP56xxx
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