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| 型號(hào)： | AD7730BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 2-CH 6-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁數(shù)： | 41/52頁 |
| 文件大?。?/td> | 497K |
| 代理商： | AD7730BRU |
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AD7730/AD7730L
REV. A
–41–
Long lead lengths from the bridge to the AD7730 facilitate the
pickup of mains frequency on the analog input, the reference
input and the power supply. T he analog inputs to the AD7730
are buffered, which allows the user to connect whatever noise
reduction capacitors are necessary in the application. T he AD7730
boasts excellent common-mode and normal- mode rejection of
mains frequency on both the analog and reference inputs. In
CHOP mode, care must be taken in choosing the output update
rate so it does not result in reducing line frequency rejection
(see DIGIT AL FILT ERING section). T he input offset current
on the AD7730 is 10 nA maximum which results in a maxi-
mum, dc offset voltage of 1.75 mV in a 350
bridge applica-
tion. Care should taken with inserting large source impedances
on the reference input pins as these inputs are not buffered and
the source impedances can result in gain errors.
In many load-cell applications, a portion of the dynamic range
of the bridge output is consumed by a pan weight or tare weight.
In such applications, the 6-bit T ARE DAC of the AD7730 can
be used to adjust out this tare weight as outlined previously.
AC E xcitation of Bridge
AC excitation of the bridge addresses many of the concerns with
thermocouple, offset and drift effects encountered in dc-excited
applications. In ac-excitation, the polarity of the excitation volt-
age to the bridge is reversed on alternate cycles. T he result is the
elimination of dc errors at the expense of a more complex sys-
tem design. Figure 24 outlines the connections for an ac-excited
bridge application based on the AD7730.
T he excitation voltage to the bridge must be switched on
alternate cycles. T ransistors T 1 to T 4 in Figure 24 perform
the switching of the excitation voltage. T hese transistors can be
discrete matched bipolar or MOS transistors, or a dedicated
bridge driver chip such as the 4427 from Micrel can be used to
perform the task.
Since the analog input voltage and the reference voltage are
reversed on alternate cycles, the AD7730 must be synchronized
with this reversing of the excitation voltage. T o allow the
AD7730 to synchronize itself with this switching, it provides the
logic control signals for the switching of the excitation voltage.
T hese signals are the nonoverlapping CMOS outputs ACX
and
ACX
.
One of the problems encountered with ac-excitation is the set-
tling time associated with the analog input signals after the
excitation voltage is switched. T his is particularly true in appli-
cations where there are long lead lengths from the bridge to the
AD7730. It means that the converter could encounter errors
because it is processing signals which are not fully settled. T he
AD7730 addresses this problem by allowing the user to program
a delay of up to 48.75
μ
s between the switching of the ACX
signals and the processing of data at the analog inputs. T his is
achieved using the DL bits of the Filter Register.
T he AD7730 also scales the ACX switching frequency in accor-
dance with the output update rate. T his avoids situations where
the bridge is switched at an unnecessarily faster rate than the
system requires.
T he fact that the AD7730 can handle reference voltages which
are the same as the excitation voltages is particularly useful in
ac-excitation where resistor divider arrangements on the
reference input add to the settling time associated with the
switching.
Figure 24. Typical Connections for AC-Excited Bridge Application
SIGMA-
DELTA
MODULATOR
AV
DD
DV
DD
AD7730
6-BIT
DAC
SERIAL INTERFACE
AND CONTROL LOGIC
REGISTER BANK
CLOCK
GENERATION
PROGRAMMABLE
DIGITAL
FILTER
SIGMA-DELTA A/D CONVERTER
BUFFER
PGA
AIN2(+)/D1
AIN2(–)/D0
ACX
ACX
STANDBY
SYNC
MCLK IN
MCLK OUT
SCLK
CS
DIN
DOUT
RESET
RDY
POL
DGND
AGND
MUX
AC
EXCITATION
CLOCK
CALIBRATION
MICROCONTROLLER
+
IN+
OUT–
IN–
OUT+
REF IN(+)
REF IN(–)
AIN1(+)
AIN1(–)
EXCITATION VOLTAGE = +5V
T4
T3
T2
T1
+/–
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7730L | Bridge Transducer ADC |
| AD7731 | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| AD7731BN | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| AD7731BR | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| AD7731BRU | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7730BRU422 | 制造商:AD 功能描述:New |
| AD7730BRU-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730BRU-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730BRUZ | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730BRUZ-REEL | 功能描述:IC ADC BRIDGE TRANSDUCER 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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