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參數(shù)資料
| 型號(hào)： | AD7730BRU |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | Bridge Transducer ADC |
| 中文描述： | 2-CH 6-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO24 |
| 封裝： | TSSOP-24 |
| 文件頁數(shù)： | 22/52頁 |
| 文件大?。?/td> | 497K |
| 代理商： | AD7730BRU |
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AD7730/AD7730L
–22–
REV. A
CALIBRAT ION OPE RAT ION SUMMARY
T he AD7730 contains a number of calibration options as outlined previously. T able X VII summarizes the calibration types, the
operations involved and the duration of the operations. T here are two methods of determining the end of calibration. T he first is to
monitor the hardware
RDY
pin using either interrupt-driven or polling routines. T he second method is to do a software poll of the
RDY
bit in the Status Register. T his can be achieved by setting up the part for continuous reads of the Status Register once a calibra-
tion has been initiated. T he
RDY
pin and
RDY
bit go high on initiating a calibration and return low at the end of the calibration
routine. At this time, the MD2, MD1, MD0 bits of the Mode Register have returned to 0, 0, 0. T he FAST and SK IP bits are treated
as 0 for the calibration sequence so the full filter is always used for the calibration routines. See Calibration section for full detail.
T able X VII. Calibration Operations
MD2, MD1,
MD0
Duration to
RDY
Low (CHP = 1)
Duration to
RDY
Low (CHP = 0)
Calibration T ype
Calibration Sequence
Internal Zero-Scale
1, 0, 0
22
×
1/Output Rate
24
×
1/Output Rate
Calibration on internal shorted input with PGA set for
selected input range. T he ac bit is ignored for this calibra-
tion sequence. T he sequence is performed with dc excitation.
T he Offset Calibration Register for the selected channel is
updated at the end of this calibration sequence. For full self-
calibration, this calibration should be preceded by an Internal
Full-Scale calibration. For applications which require an
Internal Zero-Scale and System Full-Scale calibration, this
Internal Zero-Scale calibration should be performed first.
Calibration on internally-generated input full-scale with
PGA set for selected input range. T he ac bit is ignored for
this calibration sequence. T he sequence is performed with
dc excitation. T he Gain Calibration Register for the
selected channel is updated at the end of this calibration
sequence. It is recommended that internal full-scale
calibrations are performed on the 80 mV range, regardless
of the subsequent operating range, to optimize the post-
calibration gain error. T his calibration should be followed
by either an Internal Zero-Scale or System Zero-Scale
calibration. T his zero-scale calibration should be
performed at the operating input range.
Calibration on externally applied input voltage with PGA
set for selected input range. T he input applied is assumed
to be the zero scale of the system. If ac = 1, the system
continues to use ac excitation for the duration of the
calibration. For full system calibration, this System Zero-
Scale calibration should be performed first. For applications
which require a System Zero-Scale and Internal Full-Scale
calibration, this calibration should be preceded by the
Internal Full-Scale calibration. T he Offset Calibration
Register for the selected channel is updated at the end of
this calibration sequence.
Calibration on externally-applied input voltage with PGA
set for selected input range. T he input applied is assumed
to be the full-scale of the system. If ac = 1, the system
continues to use ac excitation for the duration of the
calibration. T his calibration should be preceded by a
System Zero-Scale or Internal Zero-Scale calibration. T he
Gain Calibration Register for the selected channel is
updated at the end of this calibration sequence.
Internal Full-Scale
1, 0, 1
44
×
1/Output Rate
48
×
1/Output Rate
System Zero-Scale
22
×
1/Output Rate
24
×
1/Output Rate
System Full-Scale
1, 1, 1
22
×
1/Output Rate
24
×
1/Output Rate
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD7730L | Bridge Transducer ADC |
| AD7731 | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| AD7731BN | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| AD7731BR | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
| AD7731BRU | Low Noise, High Throughput 24-Bit Sigma-Delta ADC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7730BRU422 | 制造商:AD 功能描述:New |
| AD7730BRU-REEL | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730BRU-REEL7 | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730BRUZ | 功能描述:IC ADC TRANSDUCER BRIDGE 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD7730BRUZ-REEL | 功能描述:IC ADC BRIDGE TRANSDUCER 24TSSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
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