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參數(shù)資料
| 型號(hào)： | AD7725 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit 900 kSPS ADC with a Programmable Postprocessor |
| 中文描述： | 16位900 ksps模數(shù)轉(zhuǎn)換器的可編程后處理器 |
| 文件頁(yè)數(shù)： | 5/28頁(yè) |
| 文件大?。?/td> | 442K |
| 代理商： | AD7725 |
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REV. A
AD7725
–5–
Parameter
Symbol
Min
Typ
Max
Unit
CLKIN Frequency
CLKIN Period (t
= 1/f
CLKIN
)
CLKIN Low Pulse Width
CLKIN High Pulse Width
CLKIN Rise Time
CLKIN Fall Time
CLKIN to SCO Delay
SCO Period:
f
CLKIN
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
7
1
0.07
0.45 t
1
0.45 t
1
5
5
14.4
1
0.55 t
1
0.55 t
1
MHz
μ
s
ns
ns
ns
t
CLK
t
CLK
35
1
2
50
SCR = 0
SCR = 1
SERIAL INTERFACE (DSP MODE ONLY)
FSI Setup Time before SCO Transition
FSI Hold Time after SCO Transition
SDI Setup Time
SDI Hold Time
t
8
t
9
t
10
t
11
30
0
30
0
ns
ns
ns
ns
SERIAL INTERFACE (DSP AND BFR MODES)
SCO Transition to FSO High Delay
SCO Transition to FSO Low Delay
SDO Setup before SCO Transition
SDO Hold after SCO Transition
t
12
t
13
t
14
t
15
20
20
10
ns
ns
ns
ns
0
SERIAL INTERFACE (EPROM MODE)
SCO High Time
SCO Low Time
SOE
Low to First SCO Rising Edge
Data Setup before SCO Rising Edge
t
16
t
17
t
18
t
19
8
8
20
t
CLK
t
CLK
t
CLK
ns
22
PARALLEL INTERFACE
DATA WRITE
RS Low to
CS
Low
WR
Setup before
CS
Low
RS Hold after
CS
Rising Edge
CS
Pulse Width
WR
Hold after
CS
Rising Edge
Data Setup Time
Data Hold Time
DATA READ
RS Low to
CS
Low
RD Setup before
CS
Low
RS Hold after
CS
Rising Edge
RD Hold after
CS
Rising Edge
Data Valid after
CS
Falling Edge
3
Data Hold after
CS
Rising Edge
STATUS READ/INSTRUCTION WRITE
CS
Duty Cycle
Interrupt Clear after
CS
Low
RD Setup to
CS
Low
RD Hold after
CS
Rising Edge
Read Data Access Time
Read Data Hold after
CS
Rising Edge
Write Data Setup before
CS
Rising Edge
Write Data Hold after
CS
Rising Edge
t
20
t
21
t
22
t
23
t
24
t
25
t
26
15
15
0
50
0
10
5
ns
ns
ns
ns
ns
ns
ns
t
27
t
28
t
29
t
30
t
31
t
32
15
15
0
0
ns
ns
ns
ns
ns
ns
30
10
t
33
t
34
t
35
t
36
t
37
t
38
t
39
t
40
1
t
CLK
ns
ns
ns
ns
ns
ns
ns
15
15
0
30
10
10
5
NOTES
1
Guaranteed by design.
2
Guaranteed by characterization. All input signals are specified with tr
3
Measured with the load circuit in Figure 2 and defined as the time required for the output to cross 0.8 V and 2.4 V.
tf 5 ns (10% to 90% of DV
)
and timed from a voltage level of 1.6 V.
TIMING SPECIFICATIONS
1, 2
(AVDD = 5 V 5%; DV
DD
= 5 V 5%; AGND = DGND = 0 V, REF2= 2.5 V,
unless otherwise noted.)
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