
REV. B
AD7724
–4–
TIMING CHARACTERISTICS
1, 2
Limit at TMIN, TMAX
Parameter
(A Version)
Unit
Conditions/Comments
fMCLK
100
kHz min
Master Clock Frequency
15
MHz max
13 MHz for Specified Performance
tDELAY
14
ns max
MCLK to SCLK Delay
t1
67
ns min
Master Clock Period
t2
0.45
× t
MCLK
ns min
Master Clock Input High Time
t3
0.45
× tMCLK
ns min
Master Clock Input Low Time
t4
15
ns min
Data Hold Time After SCLK Rising Edge
t5
10
ns min
RESET Pulsewidth
t6
10
ns min
RESET Low Time Before MCLK Rising
t7
20
× tMCLK
ns max
DVAL High Delay After RESET Low
t8
3
ns max
Data Access Time After SCLK Falling Edge
t9
t3–t8
ns max
Data Valid Time Before SCLK Rising Edge
NOTES
1Sample tested at 25
°C to ensure compliance.
2Guaranteed by design.
TO
OUTPUT
PIN
CL
50pF
IOH
200 A
IOL
1.6mA
1.6V
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
t4
SCLK (O)
DATA (O)
t1
t2
t3
NOTE:
O SIGNIFIES AN OUTPUT
t8
t9
Figure 3. Data Timing
t5
MCLK (I)
RESET (I)
DVAL (O)
t6
t7
NOTE:
I SIGNIFIES AN INPUT
O SIGNIFIES AN OUTPUT
Figure 4. RESET Timing
(AVDD = 5 V
5%; DVDD = 5 V
5%; DVDD1 = 3 V
5%; AGND = DGND = 0 V, REF2A =
REF2B = 2.5 V, unless otherwise noted.)