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參數(shù)資料
| 型號(hào)： | AD7721AR |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 14/16頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT SIGMA-DELTA 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 27 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 468.75k |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 150mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 管件 |
| 輸入數(shù)目和類(lèi)型： | 1 個(gè)差分，單極；1 個(gè)差分，雙極 |
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AD7721
REV. A
–7–
Parallel Mode Only
Mnemonic
Function
CS
Chip Select Logic Input.
RD
Read Logic Input. This digital input is used in conjunction with
CS to read data from the device.
WR
Write Logic Input. This digital input is used in conjunction with
CS to write data to the control register.
DRDY
In parallel interface mode, a falling edge on
DRDY indicates that new data is available to be read from the
interface. During a synchronization or calibration cycle,
DRDY remains high until valid data is available.
DVAL/
SYNC
The function of this pin is determined by the state of bit DB3 in the control register. Writing a logic zero to
bit DB3 will program this pin to be a DVAL output. Writing a logic one to bit DB3 will program this pin to
be a
SYNC input pin.
A rising edge on
SYNC starts the synchronization cycle. SYNC must be pulsed low for at least one clock
cycle.
When switching this pin from
SYNC mode to DVAL mode, it is important that there are no rising edges on
the pin which could cause resynchronization. For this purpose, an internal pull-up resistor has been included
on this pin. Thus, when the external driver driving this pin in
SYNC mode is switched off, the DVAL/SYNC
pin remains high.
SDATA/DB11–
These pins are both data outputs and control register inputs. Output data is placed on these pins by taking
STBY/DB0
RD and CS low. Data on these pins is read into the control register by toggling WR low with CS low. With
RD high, these pins are high impedance.
Control functions such as CAL,
UNI and STBY, which are available as pins in serial mode, are available as bits in parallel mode.
Table I lists the contents of the control register onboard the AD7721. This register is written to in parallel mode using the
WR pin.
Table I. Function of Control Register Bits
Control
Register
Logical
Bit
Function
State
Mode
DB0
STBY
0
Normal Operation.
1
Power-Down (Standby) Mode.
DB1
CAL
0
Normal Operation.
1
Writing a Logic “1” to this bit starts a calibration cycle. Internal logic resets this bit to zero at the end of
calibration.
DB2
UNI
0
Unipolar Mode.
1
Bipolar Mode.
DB3
DVAL/
SYNC
0
Sets DVAL/
SYNC Pin to DVAL Mode.
1
Sets DVAL/
SYNC Pin to SYNC Mode.
DB9
0
This bit is used for testing the AD7721. A logic low MUST be written into this bit for normal
operation.
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相關(guān)代理商/技術(shù)參數(shù) |
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| AD7721AR-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 468.75ksps 16-bit Parallel/Serial 28-Pin SOIC W T/R |
| AD7721ARZ | 功能描述:IC ADC 16BIT SIGMA-DELTA 28SOIC RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 其它有關(guān)文件:TSA1204 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:- 位數(shù):12 采樣率（每秒）:20M 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:155mW 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:48-TQFP 供應(yīng)商設(shè)備封裝:48-TQFP（7x7） 包裝:Digi-Reel® 輸入數(shù)目和類(lèi)型:4 個(gè)單端，單極；2 個(gè)差分，單極 產(chǎn)品目錄頁(yè)面:1156 (CN2011-ZH PDF) 其它名稱(chēng):497-5435-6 |
| AD7721ARZ-REEL | 功能描述:IC ADC 16BIT SIGMA-DELTA 28SOIC RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類(lèi)型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD7721SQ | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC |
| AD7722 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:16-Bit, 195 kSPS CMOS, Sigma-Delta ADC |
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