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參數(shù)資料
| 型號(hào)： | AD7720BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MODULATOR SIGMA-DELTA 28TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 12.5M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 215mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個(gè)差分，單極；1 個(gè)差分，雙極 |
AD7720
–12–
REV. 0
12pF
1k
12pF
1k
220nF
374k
1nF
VIN(–)
1/2
OP275
VIN(+)
REF1
REF2
100nF
DIFFERENTIAL
INPUT = 2.5V p-p
VIN(–) BIAS
VOLTAGE = 1.25V
AIN =
1.25V
1/2
OP275
1k
374k
10nF
1nF
Figure 28. Single-Ended Analog Input for Bipolar Mode
Operation
12pF
1k
AIN =
0.625V
1k
12pF
1k
1/2
OP275
220nF
R
1nF
VIN(–)
1nF
1/2
OP275
VIN(+)
DIFFERENTIAL
INPUT = 2.5V p-p
COMMON MODE
VOLTAGE = 2.5V
REF1
OP07
REF2
100nF
Figure 29. Single-Ended to Differential Analog Input
Circuit for Bipolar Mode Operation
The 1 nF capacitors at each ADC input store charge to aid the
amplifier settling as the input is continuously switched. A resis-
tor in series with the drive amplifier output and the 1 nF input
capacitor may also be used to create an antialias filter.
Clock Generation
The AD7720 contains an oscillator circuit to allow a crystal or
an external clock signal to generate the master clock for the
ADC. The connection diagram for use with the crystal is shown
in Figure 30. Consult the crystal manufacturer’s recommenda-
tion for the load capacitors.
1M
XTAL
MCLK
Figure 30. Crystal Oscillator Connection
An external clock must be free of ringing and have a minimum
rise time of 5 ns. Degradation in performance can result as high
edge rates increase coupling that can generate noise in the sam-
pling process. The connection diagram for an external clock
source (Figure 31) shows a series damping resistor connected
between the clock output and the clock input to the AD7720.
The optimum resistor will depend on the board layout and the
impedance of the trace connecting to the clock input.
CLOCK
CIRCUITRY
MCLK
25–150
Figure 31. External Clock Oscillator Connection
A low phase noise clock should be used to generate the ADC
sampling clock because sampling clock jitter effectively modu-
lates the input signal and raises the noise floor. The sampling
clock generator should be isolated from noisy digital circuits,
grounded and heavily decoupled to the analog ground plane.
The sampling clock generator should be referenced to the ana-
log ground plane in a split ground system. However, this is not
always possible because of system constraints. In many cases,
the sampling clock must be derived from a higher frequency
multipurpose system clock that is generated on the digital
ground plane. If the clock signal is passed between its origin on
a digital plane to the AD7720 on the analog ground plane, the
ground noise between the two planes adds directly to the clock
and will produce excess jitter. The jitter can cause unwanted
degradation in the signal-to-noise ratio and also produce un-
wanted harmonics.
This can be somewhat remedied by transmitting the sampling
clock signal as a differential one, using either a small RF trans-
former or a high speed differential driver and receiver such as
PECL. In either case, the original master system clock should
be generated from a low phase noise crystal oscillator.
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| AD7721 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC |
| AD7721AN | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 468.75ksps 16-bit Parallel/Serial 28-Pin PDIP W |
| AD7721ANZ | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 468.75ksps 16-bit Parallel/Serial 28-Pin PDIP W |
| AD7721AR | 功能描述:IC ADC 16BIT SIGMA-DELTA 28-SOIC RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD7721AR-REEL | 制造商:Analog Devices 功能描述:ADC Single Delta-Sigma 468.75ksps 16-bit Parallel/Serial 28-Pin SOIC W T/R |
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