
AD7720
–4–
REV. 0
TIMING CHARACTERISTICS (AVDD = +5 V 5%; DVDD = +5 V 5%; AGND = DGND = 0 V, REF2= +2.5 V unless otherwise noted)
Limit at TMIN, TMAX
Parameter
(B Version)
Units
Conditions/Comments
fMCLK
100
kHz min
Master Clock Frequency
15
MHz max
12.5 MHz for Specified Performance
t1
67
ns min
Master Clock Period
t2
0.45
× t
MCLK
ns min
Master Clock Input High Time
t3
0.45
× t
MCLK
ns min
Master Clock Input Low Time
t4
15
ns min
Data Hold Time After SCLK Rising Edge
t5
10
ns min
RESET Pulsewidth
t6
10
ns min
RESET Low Time Before MCLK Rising
t7
20
× t
MCLK
ns max
DVAL High Delay after RESET Low
NOTE
Guaranteed by design.
IOL
1.6mA
IOH
200 A
+1.6V
CL
50pF
TO
OUTPUT
PIN
Figure 2. Load Circuit for Access Time and Bus Relinquish Time
SCLK (O)
DATA (O)
t1
t2
t3
t4
NOTE:
O SIGNIFIES AN OUTPUT
Figure 3. Data Timing
t5
MCLK (I)
RESET (I)
DVAL (O)
t6
t7
NOTE:
I SIGNIFIES AN INPUT
O SIGNIFIES AN OUTPUT
Figure 4. RESET Timing