參數(shù)資料
型號： AD7719BR-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 25/40頁
文件大?。?/td> 0K
描述： IC ADC 16BIT 24BIT DUAL 28-SOIC
標準包裝： 1,000
位數(shù)： 16/24
采樣率（每秒）： 105
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 4.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 28-SOIC W
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 3 個差分，單極；3 個差分，雙極
REV. A
AD7719
–31–
Analog Input Channels
The main ADC has four associated analog input pins (labeled
AIN1 to AIN4) that can be configured as two fully differential
input channels or three pseudodifferential input channels.
Channel selection bits CH1 and CH0 in the ADC0CON
register, along with the CHCON bit of the mode register,
detail the different configurations.
The auxiliary ADC has four external input pins (labeled AIN3
to AIN6) as well as an internal connection to the internal on-chip
temperature sensor. Channel selection bits ACH2, ACH1, and
ACH0 in the ADC1CON register, along with the CHCON
bit in the mode register, detail the various configurations on
these input channels.
Two input multiplexers (MUX1 and MUX2) switch the selected
input channel to the on-chip buffer amplifier in the case of the
main ADC when operated in buffered mode, and directly to the
Σ- modulator input in the case of the auxiliary ADC and when
the main ADC is operated in unbuffered mode. When the analog
input channel is switched, the settling time of the part must elapse
before a new valid word is available from the ADC.
Figure 16 shows the analog input channel configurations available
to the user when the CHCON bit in the mode register is set to a
zero. In this case, the main ADC can be configured as one or two
fully differential input channels (AIN1/AIN2 and AIN3/AIN4)
and the aux can be configured as two single-ended inputs with
respect to AGND (AIN3/AGND and AIN4/AGND) and one fully
differential input AIN5/AIN6). The aux can also be configured as
three single-ended inputs with respect to AGND (AIN3/AGND,
AIN4/AGND, and AIN5/AGND) by tying AIN6 externally to
AGND. The temp sensor is available as an internal connection.
SINGLE-
ENDED
INPUT
SINGLE-
ENDED
INPUT
FULLY DIFFERENTIAL
AIN(+)
AIN(–)
AIN(+)
AIN(–)
AIN1
AIN2
AIN3
AIN4
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN3
AIN4
AGND
MUX1
(MAIN ADC)
(AUX ADC)
AIN5
AIN6
MAIN CHANNEL
AUX CHANNEL
MUX2
Figure 16. Input Channel Configurations with CHCON = 0
Figure 17 shows the analog input channel configurations avail-
able to the user when the CHCON bit in the mode register is
set to 1. In this case, the main ADC is configured as three
pseudodifferential input channels (AIN1/AIN4, AIN2/AIN4, and
AIN3/AIN4) and the aux can be configured as two single-ended
inputs with respect to AGND (AIN5/AGND and AIN6/AGND)
and one fully differential input (AIN5/AIN6). The temp sensor
is available as an internal connection.
SINGLE-
ENDED
INPUT
FULLY DIFFERENTIAL
AIN(+)
AIN(–)
AIN(+)
AIN(–)
AIN1
AIN2
AIN3
AIN4
AIN1
AIN2
AIN3
AIN4
AIN5
AIN6
AIN3
AIN4
AGND
MUX1
(MAIN ADC)
(AUX ADC)
AIN5
AIN6
SINGLE-
ENDED
INPUT
AIN3/AIN4
AIN2/AIN4
AIN1/AIN4
MUX2
MAIN CHANNEL
AUX CHANNEL
PSEUDO-
DIFFERENTIAL
INPUT
PSEUDO-
DIFFERENTIAL
INPUT
Figure 17. Input Channel Configurations with CHCON = 1
In buffered mode (
BUF = 0), the output of the main ADC multi-
plexer feeds into a high impedance input stage of the buffer
amplifier. As a result, the main ADC inputs can handle significant
source impedances and are tailored for direct connection to
external resistive-type sensors like strain gages or resistance
temperature detectors (RTDs).
The auxiliary ADC and the main ADC when operated with
BUF = 1, however, are unbuffered, resulting in higher analog
input current. It should be noted that these unbuffered input
paths provide a dynamic load to the driving source. Therefore,
resistor/capacitor combinations on the input pins can cause dc
gain errors, depending on the output impedance of the source
that is driving the ADC inputs. Table XVIII and XIX show the
allowable external resistance/capacitance values for unbuffered
mode such that no gain error at the 16- and 20-bit level,
respectively, is introduced.
The absolute input voltage range on the main ADC when oper-
ated in buffered mode is restricted to a range between AGND +
100 mV and AVDD – 100 mV. Care must be taken in setting up
the common-mode voltage and input voltage range so that these
limits are not exceeded; otherwise there will be a degradation in
linearity and noise performance.
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