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參數(shù)資料
| 型號(hào)： | AD7719BR-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 19/40頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 24BIT DUAL 28-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 16/24 |
| 采樣率（每秒）： | 105 |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 4.5mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 28-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類(lèi)型： | 3 個(gè)差分，單極；3 個(gè)差分，雙極 |
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REV. A
AD7719
–26–
Main ADC Data Result Registers (DATA0): (A3, A2, A1, A0 =
0, 1, 0, 1; Power-On Reset = 0x00 0000)
The conversion results for the main ADC channel are stored in
the main ADC data register (DATA0). This register is either 16
or 24 bits wide, depending on the status of the WL bit in the
main ADC control register (AD0CON). This is a read-only
register. On completion of a read from this register, the RDY0
bit in the status register is cleared.
Aux ADC Data Result Registers (DATA1): (A3, A2, A1, A0 = 0,
1, 1, 0; Power-On Reset = 0x0000)
The conversion results for the aux ADC channel are stored in
the aux ADC data register (DATA1). This register is 16 bits
wide and is a read-only register. On completion of a read from
this register, the RDY1 bit in the status register is cleared.
Main ADC Offset Calibration Coefficient Registers (OF0):
(A3, A2, A1, A0 = 1, 0, 0, 0; Power-On Reset = 0x80 0000)
The offset calibration registers hold the 24-bit data offset
calibration coefficient for the main ADC. There are three
registers associated with the main ADC channel. In fully
differential operating mode, there are two input channels and a
register is dedicated to each input. When operating in
pseudodifferential mode, the main ADC can be configured for
three input channels and there is a dedicated register for each
pseudodifferential input. These registers have a power-on reset
value of 0x80 0000. The channel bits, in association with the
communication register address for the OF0 register, allow
access to these registers. These registers are read/write registers.
The calibration registers can only be written to if the ADC is
inactive (MD bits in the mode register = 000 or 001 or both
AD0EN and AD1EN bits in the control registers are cleared).
Reading of the calibration registers does not clear the RDY0 bit.
Aux ADC Offset Calibration Coefficient Registers (OF1):
(A3, A2, A1, A0 = 1, 0, 0, 1; Power-On Reset = 0x8000)
The offset calibration register OF1 holds the 16-bit data offset
calibration coefficient for the aux ADC. This register has a power-
on-reset value of 0x8000. The channel bits, in association with
the communication register address for the OF1 register, allow
access to these registers. These registers are read/write registers.
The calibration registers can only be written to if the ADC is
inactive (MD bits in the mode register = 000 or 001 or both
AD0EN and AD1EN bits in the control registers are cleared).
Reading of the calibration registers does not clear the RDY1 bit.
Main ADC Gain Calibration Coefficient Registers (GNO):
(A3, A2, A1, A0 = 1, 0, 1, 0; Power-On Reset = 0x5X XXX5)
The gain calibration registers hold the 24-bit data gain calibration
coefficient for the main ADC. These registers are configured at
power-on with factory calculated internal full-scale calibration
coefficients. Every device will have different coefficients. However,
these bytes will be automatically overwritten if an internal or
system full-scale calibration is initiated by the user via MD2–0 bits
in the Mode register. There are three gain calibration registers
associated with the main ADC channel. In fully differential
operating mode, there are two input channels and a register is
dedicated to each input. When operating in pseudodifferential
mode, the main ADC can be configured for three input channels
and there is a dedicated register for each pseudodifferential
input. These registers are read/write registers. The calibration
registers can only be written to if the ADC is inactive (MD bits
in the mode register = 000 or 001 or both AD0EN and AD1EN
bits in the control registers are cleared). Reading of the
calibration registers does not clear the RDY1 bit.
Aux ADC Gain Calibration Coefficient Registers (GN1): (A3,
A2, A1, A0 = 1, 0, 1, 1; Power-On Reset = 0x59XX)
The gain calibration register GN1 holds the 16-bit data gain
calibration coefficient for the aux ADC. This register is configured
at power-on with factory calculated internal zero-scale calibration
coefficients. Every device will have different coefficients. However,
these coefficients will be automatically overwritten if an internal
or system zero-scale calibration is initiated by the user via the
MD2–0 bits in the Mode register. These registers are read/write
registers. The calibration registers can only be written to if the
ADC is inactive (MD bits in the mode register = 000 or 001 or
both AD0EN and AD1EN bits in the control registers are cleared).
Reading of the calibration registers does not clear the RDY1 bit.
ID Register (ID): (A3, A2, A1, A0 = 1, 1, 1, 1; Power-On
Reset = 0x0X)
This register is a read-only 8-bit register. The contents are used
to determine the die revision of the AD7719. Table XVII
indicates the bit locations.
User Nonprogrammable Test Registers
The AD7719 contains two test registers. The bits in this test
register control the test modes of the AD7719, which are used
for the testing of the device. The user is advised not to change the
contents of these registers.
Table XVII. ID Register Bit Designations
7
D
I6
D
I5
D
I4
D
I3
D
I2
D
I1
D
I0
D
I
0
000
XXXX
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