AVDD = 3 V to 5 V, DVDD
參數(shù)資料
型號： AD7715ARU-5
廠商： Analog Devices Inc
文件頁數(shù)： 38/40頁
文件大?。?/td> 0K
描述： IC ADC 16BIT SIGMA-DELTA 16TSSOP
標準包裝： 1
位數(shù)： 16
采樣率（每秒）： 500
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉換器數(shù)目： 1
功率耗散（最大）： 9.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 16-TSSOP（0.173"，4.40mm 寬）
供應商設備封裝： 16-TSSOP
包裝： 管件
輸入數(shù)目和類型： 1 個差分，單極；1 個差分，雙極
配用： EVAL-AD7715-3EBZ-ND - BOARD EVALUATION FOR AD7715
AD7715
Rev. D | Page 7 of 40
AVDD = 3 V to 5 V, DVDD = 3 V to 5 V, REF IN(+) = 1.25 V (AD7715-3) or 2.5 V (AD7715-5); REF IN() = AGND; MCLK IN = 1 MHz to
2.4576 MHz, unless otherwise noted. All specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter
Min
Typ
Max
Unit
Conditions/Comments
SYSTEM CALIBRATION
Positive Full-Scale Calibration Limit1
(1.05 ×
VREF)/GAIN
V
GAIN Is the selected PGA gain (1, 2, 32, or 128)
Negative Full-Scale Calibration Limit1
(1.05 ×
VREF)/GAIN
V
GAIN Is the selected PGA gain (1, 2, 32, or 128)
Offset Calibration Limit2
(1.05 ×
VREF)/GAIN
V
GAIN Is the selected PGA gain (1, 2, 32, or 128)
Input Span2
0.8 ×
VREF/GAIN
V
GAIN Is the selected PGA gain (1, 2, 32, or 128)
(2.1 × VREF)/GAIN
V
GAIN Is the selected PGA gain (1, 2, 32, or 128)
POWER REQUIREMENTS
Power Supply Voltages
AVDD Voltage (AD7715-3)
3
3.6
V
For specified performance
AVDD Voltage (AD7715-5)
4.75
5.25
V
For specified performance
DVDD Voltage
3
5.25
V
For specified performance
Power Supply Currents
AVDD Current
AVDD = 3.3 V or 5 V. gain = 1 to 128 (fCLK IN = 1 MHz) or
gain = 1 or 2 (fCLK IN = 2.4576 MHz)
0.27
mA
Typically 0.2 mA; BUF bit of the setup register = 0
0.6
mA
Typically 0.4 mA; BUF bit of the setup register = 1, AVDD
= 3.3 V or 5 V; gain = 32 or 128 (fCLK IN = 2.4576 MHz)3
0.5
mA
Typically 0.3 mA; BUF bit of the setup register = 0
1.1
mA
Typically 0.8 mA; BUF bit of the setup register = 1
DVDD Current4
Digital inputs = 0 V or DVDD; external MCLK IN
0.18
mA
Typically 0.15 mA. DVDD = 3.3 V. fCLK IN = 1 MHz
0.4
mA
Typically 0.3 mA. DVDD = 5 V. fCLK IN = 1 MHz
0.5
mA
Typically 0.4 mA. DVDD = 3.3 V. fCLK IN = 2.4576 MHz
0.8
mA
Typically 0.6 mA. DVDD = 5 V. fCLK IN = 2.4576 MHz
Power Supply Rejection5
Depends on gain6
dB
Normal-Mode Power Dissipation4
AVDD = DVDD = 3.3 V; digital inputs = 0 V or DVDD; external
MCLK IN
1.5
mW
BUF bit = 0. all gains 1 MHz clock
2.65
mW
BUF bit = 1. all gains 1 MHz clock
3.3
mW
BUF bit = 0. Gain = 32 or 128 @ fCLK IN = 2.4576 MHz
5.3
mW
BUF bit = 1. Gain = 32 or 128 @ fCLK IN = 2.4576 MHz
Normal-Mode Power Dissipation4
AVDD = DVDD = 5 V. digital inputs = 0 V or DVDD; external
MCLK IN
3.25
mW
BUF bit = 0; all gains 1 MHz clock
5
mW
BUF bit = 1; all gains 1 MHz clock
6.5
mW
BUF bit = 0; gain = 32 or 128 @ fCLK IN = 2.4576 MHz
9.5
mW
BUF bit = 1; gain = 32 or 128 @ fCLK IN = 2.4576 MHz
Standby (Power-Down) Current7
20
μA
External MCLK IN = 0 V or DVDD. typically 10 μA; VDD = 5 V
Standby (Power-Down) Current7
10
μA
External MCLK IN = 0 V or DVDD. typically 5 μA; VDD = 3.3 V
1 After calibration, if the analog input exceeds positive full scale, the converter outputs all 1s. If the analog input is less than negative full scale, then the device outputs
all 0s.
2 These calibration and span limits apply provided the absolute voltage on the analog inputs does not exceed AVDD + 30 mV or go more negative than AGND 30 mV.
The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
3 Assumes CLK Bit of setup register is set to correct status corresponding to the master clock frequency.
4 When using a crystal or ceramic resonator across the MCLK pins as the clock source for the device, the DVDD current and power dissipation will vary depending on the
crystal or resonator type (see the Clocking and Oscillator Circuit section).
5 Measured at dc and applies in the selected pass-band. PSRR at 50 Hz exceeds 120 dB with filter notches of 25 Hz or 50 Hz. PSRR at 60 Hz exceeds 120 dB with filter
notches of 20 Hz or 60 Hz.
6 PSRR depends on gain. Gain of 1:85 dB typical; gain of 2:90 dB typical; gains of 32 and 128:95 dB typical.
7 If the external master clock continues to run in standby mode, the standby current increases to 50 μA typical. When using a crystal or ceramic resonator across the
MCLK pins as the clock source for the device, the internal oscillator continues to run in standby mode and the power dissipation depends on the crystal or resonator
type (see the Standby Mode section).
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