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參數(shù)資料
| 型號： | AD7703CR-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 20BIT LC2MOS MONO 20-SOIC |
| 標準包裝： | 1,000 |
| 位數(shù)： | 20 |
| 采樣率（每秒）： | 4k |
| 數(shù)據(jù)接口： | 串行 |
| 轉換器數(shù)目： | 1 |
| 功率耗散（最大）： | 37mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 20-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 20-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個單端，雙極 |
REV. E
–14–
AD7703
Synchronous Self-Clocking Mode (SSC)
The SSC mode (MODE pin high) allows easy interfacing to
serial-parallel conversion circuits in systems with parallel data
communication. This mode allows interfacing to 74XX299
Universal Shift registers without any additional decoding. The
SSC mode can also be used with microprocessors such as the
68HC11 and 68HC05, which allow an external device to clock
their serial port.
Figure 15 shows the timing diagram for the SSC mode. Data is
clocked out by an internally generated serial clock. The AD7703
divides each sampling interval into 16 distinct periods. Eight
periods of 64 clock pulses are for analog settling and eight peri-
ods of 64 clock pulses are for digital computation. The status of
CS is polled at the beginning of each digital computation period. If
it is low at any of these times, then SCLK will become active
and the data-word currently in the output register will be trans-
mitted, MSB first. After the LSB has been transmitted,
DRDY
will go high until the new data-word becomes available. If
CS,
having been brought low, is taken high again at any time during
data transmission, SDATA and SCLK will go three-state after
the current bit finishes. If
CS is subsequently brought low,
transmission will resume with the next bit during the subse-
quent digital computation period. If transmission has not been
initiated and completed by the time the next data-word is avail-
able,
DRDY will go high for four clock cycles then low again as
the new word is loaded into the output register.
A more detailed diagram of the data transmission in the SSC
mode is shown in Figure 16. Data bits change on the falling
edge of SCLK and are valid on the rising edge of SCLK.
ANALOG TIME 0
DIGITAL TIME 7
SCLK (O)
SDATA (O)
HI-Z
MSB
DRDY (O)
DIGITAL TIME 0
CS POLLED
CS (I)
INTERNAL
STATUS
72 CLKIN CYCLES
64 CLKIN
CYCLES
64 CLKIN
CYCLES
1024 CLKIN CYCLES
LSB
Figure 15. Timing Diagram for SSC Transmission Mode
CLKIN (I)
DRDY (O)
SDATA (O)
DB19 (MSB)
DB18
DB2
DB1
DB0 (LSB)
HI-Z
SCLK (O)
HI-Z
CS (I)
72
CLKIN
CYCLES
DB17
Figure 16. SSC Mode Showing Data Timing Relative to SCLK
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD7703CRZ | 功能描述:IC ADC 20BIT LC2MOS MONO 20SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1 系列:- 位數(shù):14 采樣率（每秒）:83k 數(shù)據(jù)接口:串行，并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:95mW 電壓電源:雙 ± 工作溫度:0°C ~ 70°C 安裝類型:通孔 封裝/外殼:28-DIP（0.600"，15.24mm） 供應商設備封裝:28-PDIP 包裝:管件 輸入數(shù)目和類型:1 個單端，雙極 |
| AD7703SQ | 制造商:AD 制造商全稱:Analog Devices 功能描述:LC2MOS 20-Bit A/D Converter |
| AD7705 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, 1 mW 2-/3-Channel 16-Bit, Sigma-Delta ADCs |
| AD7705_06 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3 V/5 V, 1 mW, 2-/3-Channel, 16-Bit, Sigma-Delta ADCs |
| AD7705BN | 功能描述:IC ADC 16BIT 2CH 16-DIP RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類型:2 個單端，單極 |
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