參數(shù)資料
型號(hào): AD7690
廠商: Analog Devices, Inc.
英文描述: 16-Bit, +/-0.65 LSB INL, 500 kSPS PulSAR Differential ADC in MSOP/QFN
中文描述: 16位/ -0.65 LSB INL和500 kSPS的PulSAR系列差分ADC,采用MSOP / QFN封裝
文件頁數(shù): 20/24頁
文件大?。?/td> 449K
代理商: AD7690
AD7693
Preliminary Technical Data
CS MODE 4-WIRE WITH BUSY INDICATOR
Rev. PrB | Page 20 of 24
This mode is usually used when a single AD7693 is connected
to an SPI-compatible digital host, which has an interrupt input,
and it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in
applications where low jitter on CNV is desired.
The connection diagram is shown in Figure 39, and the
corresponding timing is given in Figure 40.
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback. (If SDI and CNV are low, SDO is
driven low.) Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time elapses and then held low for the maximum possible
conversion time to guarantee the generation of the busy signal
indicator. When the conversion is complete, SDO goes from
high impedance to low impedance. With a pull-up on the SDO
line, this transition can be used as an interrupt signal to initiate
the data readback controlled by the digital host. The AD7693
then enters the acquisition phase and powers down. The data
bits are clocked out, MSB first, by subsequent SCK falling edges.
The data is valid on both SCK edges. Although the rising edge
can be used to capture the data, a digital host using the SCK
falling edge will allow a faster reading rate, provided it has an
acceptable hold time. After the optional 17
th
SCK falling edge,
or SDI going high, whichever is earlier, SDO returns to high
impedance.
DATA IN
IRQ
CLK
CONVERT
CS1
VIO
DIGITAL HOST
CNV
SCK
SDO
SDI
AD7693
-
CS
Figure 39. 4-Wire
Mode with Busy Indicator Connection Diagram
SDO
D15
D14
D1
D0
t
DIS
SCK
1
2
3
15
16
17
t
SCK
t
SCKL
t
SCKH
t
HSDO
t
DSDO
t
EN
CONVERSION
ACQUISITION
t
CONV
t
CYC
t
ACQ
ACQUISITION
SDI
CNV
t
SSDICNV
t
HSDICNV
-
CS
Figure 40. 4-Wire
Mode with Busy Indicator Serial Interface Timing
相關(guān)PDF資料
PDF描述
AD7693 16-Bit, +/-0.65 LSB INL, 500 kSPS PulSAR Differential ADC in MSOP/QFN
ADA4941-1 16-Bit, +/-0.65 LSB INL, 500 kSPS PulSAR Differential ADC in MSOP/QFN
AD7691 18-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN
AD7691BRMZ 18-Bit, 1.5 LSB INL, 250 kSPS PulSAR Differential ADC in MSOP/QFN
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