參數(shù)資料
型號： AD7686CCPZRL7
廠商： Analog Devices Inc
文件頁數(shù)： 13/28頁
文件大?。?/td> 0K
描述： IC ADC 16BIT SAR 500KSPS 10LFCSP
標(biāo)準(zhǔn)包裝： 1
系列： PulSAR®
位數(shù)： 16
采樣率（每秒）： 500k
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 21.5mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 10-WFDFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 10-LFCSP-WD（3x3）
包裝： 標(biāo)準(zhǔn)包裝
輸入數(shù)目和類型： 1 個偽差分，單極
產(chǎn)品目錄頁面： 778 (CN2011-ZH PDF)
其它名稱： AD7686CCPZRL7DKR
AD7686
Rev. B | Page 20 of 28
CS MODE 4-WIRE WITH BUSY INDICATOR
This mode is usually used when a single AD7686 is connected
to an SPI-compatible digital host, which has an interrupt input,
and when it is desired to keep CNV, which is used to sample the
analog input, independent of the signal used to select the data
reading. This requirement is particularly important in applications
where low jitter on CNV is desired. The connection diagram is
shown in Figure 39, and the corresponding timing is provided
With SDI high, a rising edge on CNV initiates a conversion,
selects the CS mode, and forces SDO to high impedance. In this
mode, CNV must be held high during the conversion phase and
the subsequent data readback (if SDI and CNV are low, SDO is
driven low). Prior to the minimum conversion time, SDI can be
used to select other SPI devices, such as analog multiplexers,
but SDI must be returned low before the minimum conversion
time and held low until the maximum conversion time to
guarantee the generation of the busy signal indicator. When
conversion is complete, SDO goes from high impedance to low.
With a pull-up on the SDO line, this transition can be used as
an interrupt signal to initiate the data readback controlled by
the digital host. The AD7686 then enters the acquisition phase
and powers down. The data bits are then clocked out, MSB first,
by subsequent SCK falling edges. The data is valid on both SCK
edges. Although the rising edge can be used to capture the data,
a digital host using the SCK falling edge allows a faster reading
rate, provided it has an acceptable hold time. After the optional
17th SCK falling edge or SDI going high, whichever occurs first,
the SDO returns to high impedance.
DATA IN
IRQ
CLK
CONVERT
CS1
VIO
DIGITAL HOST
02
96
9-
04
0
47k
CNV
SCK
SDO
SDI
AD7686
Figure 39. CS Mode 4-Wire with Busy Indicator Connection Diagram
SDO
D15
D14
D1
D0
tDIS
SCK
1
2
3
151617
tSCK
tSCKL
tSCKH
tHSDO
tDSDO
tEN
CONVERSION
ACQUISITION
tCONV
tCYC
tACQ
ACQUISITION
SDI
CNV
tSSDICNV
tHSDICNV
02
96
9-
0
41
Figure 40. CS Mode 4-Wire with Busy Indicator Serial Interface Timing
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