VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, T
參數(shù)資料
型號: AD7685CRMZRL7
廠商: Analog Devices Inc
文件頁數(shù): 23/28頁
文件大?。?/td> 0K
描述: IC ADC 16BIT PSEUDO-DIFF 10MSOP
產(chǎn)品培訓(xùn)模塊: Power Line Monitoring
Motor Control
設(shè)計資源: Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104)
Integrated Device Power Supply for PAD with Output Voltage Range 0 V to 25 V (CN0130)
標準包裝: 1,000
系列: PulSAR®
位數(shù): 16
采樣率(每秒): 250k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 15mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個偽差分,單極
配用: EVAL-AD7685CBZ-ND - BOARD EVAL FOR AD7685
AD7685
Rev. C | Page 4 of 28
VDD = 2.3 V to 5.5 V, VIO = 2.3 V to VDD, VREF = VDD, TA = –40°C to +85°C, unless otherwise noted.
Table 3.
Parameter
Conditions
Min
Typ
Max
Unit
REFERENCE
Voltage Range
0.5
VDD + 0.3
V
Load Current
250 kSPS, REF = 5 V
50
μA
SAMPLING DYNAMICS
3 dB Input Bandwidth
2
MHz
Aperture Delay
VDD = 5 V
2.5
ns
DIGITAL INPUTS
Logic Levels
VIL
–0.3
0.3 × VIO
V
VIH
0.7 × VIO
VIO + 0.3
V
IIL
1
+1
μA
IIH
1
+1
μA
DIGITAL OUTPUTS
Data Format
Serial 16 bits straight binary
Pipeline Delay
Conversion results available immediately
after completed conversion
VOL
ISINK = +500 μA
0.4
V
VOH
ISOURCE = 500 μA
VIO 0.3
V
POWER SUPPLIES
VDD
Specified performance
2.3
5.5
V
VIO
Specified performance
2.3
VDD + 0.3
V
VIO Range
1.8
VDD + 0.3
V
Standby Current1, 2
VDD and VIO = 5 V, 25°C
1
50
nA
Power Dissipation
VDD = 2.5 V, 100 SPS throughput
1.4
μW
VDD = 2.5 V, 100 kSPS throughput
1.35
2.4
mW
VDD = 2.5 V, 200 kSPS throughput
2.7
4.8
mW
VDD = 5 V, 100 kSPS throughput
4
6
mW
VDD = 5 V, 250 kSPS throughput
10
15
mW
TEMPERATURE RANGE3
Specified Performance
TMIN to TMAX
40
+85
°C
1 With all digital inputs forced to VIO or GND as required.
2 During acquisition phase.
3 Contact sales for extended temperature range.
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