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參數(shù)資料
| 型號： | AD768-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 30 MSPS D/A Converter |
| 中文描述： | 16位，30 MSPS的D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 5/20頁 |
| 文件大?。?/td> | 334K |
| 代理商： | AD768-EB |
AD768
REV. B
–5–
T emperature Drift
T emperature drift is specified as the maximum change from the
ambient (+25
°
C) value to the value at either T
MIN
or T
MAX
. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is re-
ported in ppm per degree C.
Power Supply Rejection
T he maximum change in the full-scale output as the supplies
are varied from nominal to minimum and maximum specified
voltages.
Settling T ime
T he time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Spurious-Free Dynamic Range
T he difference, in dB, between the rms amplitude of the
input signal and the peak spurious signal over the specified
bandwidth.
T otal Harmonic Distortion
T HD is the ratio of the rms sum of the first six harmonic com-
ponents to the rms value of the measured input signal. It is ex-
pressed as a percentage or in decibels (dB).
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients which are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-sec.
DE FINIT IONS OF SPE CIFICAT IONS
Linearity E rror (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the ac-
tual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a1 LSB changein digital input code.
Monotonicity
A D/A converter is monotonic if the output either increases or
remains constant as the digital input increases.
Offset E rror
T he deviation of the output current from the ideal of zero is
called offset error. For IOUT A, 0 mA output is expected when
the inputs are all 0s. For IOUT B, 0 mA output is expected
when all inputs are set to 1s.
Gain E rror
T he difference between the actual and ideal output span. T he
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s. T he ideal
output current span is4
×
thecurrent applied to the IREFIN pin.
Output Compliance Range
T he range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
5mA
6
C
REFCOMP
1μF
R
REF
500
REFIN
REFOUT
NC
V
DD
3
4
+2.5V REF
25
5
REFCOM
1μF
C
NR
2
NR
V
EE
26
15
1μF
1μF
+5V
–5V
DCOM
R
LAD
1k
R
LAD
1k
LADCOM
IOUTA
IOUTB
1
28
27
50
R
LOAD
50
IOUTA
IOUTB
SEGMENTED
CURRENT
SOURCES
CURRENT SOURCES
AND R-2R LADDER
CLOCK
21
22
23
24
19
20
13
14
17
18
7
8
9
10
11
12
LATCHES – LOWER 12 BITS
16
MSB DECODE
& LATCHES
CLOCK
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
D
AD768
Figure 1. Functional Block Diagram and Basic Hookup
FUNCT IONAL DE SCRIPT ION
T he AD768 is a current-output DAC with a nominal full-scale
current of 20 mA and a 1 k
output impedance. Differential
outputs are provided to support single-ended or differential
applications. T he DAC architecture combines segmented cur-
rent sources for the top four bits (MSBs) and a 1 k
R-2R lad-
der for the lower 12 bits (LSBs). T he DAC current sources are
implemented with laser-trimmable thin film resistors for excel-
lent dc linearity. A proprietary switching technique is utilized to
reduce glitch energy and maximize dynamic accuracy.
T he digital interface offers CMOS compatible edge-triggered
input latches that interface readily to CMOS logic and supports
clock rates up to 40 MSPS. A temperature compensated 2.5 V
bandgap reference is integrated on-chip to drive the AD768 ref-
erence input current with the use of a single external resistor.
T he functional block diagram in Figure 1 is a simple representa-
tion of the internal circuitry to aid the understanding of the
AD768’s operation. T he DAC transfer function is described,
and followed by a detailed description of each key portion of the
circuit. T ypical circuit configurations are shown in the section
APPLYING T HE AD768.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| AD768-EBZ | 制造商:Analog Devices 功能描述:EVAL BOARD - Boxed Product (Development Kits) |
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| AD76901 | 制造商:AD 制造商全稱:Analog Devices 功能描述:14-Bit, 500 kSPS PulSAR ADC in MSOP |
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