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參數(shù)資料
| 型號(hào)： | AD768-EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 16-Bit, 30 MSPS D/A Converter |
| 中文描述： | 16位，30 MSPS的D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大小： | 334K |
| 代理商： | AD768-EB |
REV. B
–10–
AD768
APPLYING T HE AD768
OUT PUT CONFIGURAT IONS
T he following sections illustrate some typical output configura-
tions for the AD768. While most figures take the output at
IOUT A, IOUT B can be interchanged in all cases. Unless other-
wise noted, it is assumed that I
REFIN
and full-scale currents are
set to nominal values.
For application that require the specified dc accuracies, proper
resistor selection is required. In addition to absolute resistor tol-
erances, resistor self-heating can result in unexpected errors. For
optimal INL, the buffered voltage output is recommended as
shown in Figure 23. In this configuration, self-heating of R
FB
may cause a change in gain, producing a bow in the INL curve.
T his effect can be minimized by selection of a low temperature
coefficient resistor.
UNBUFFE RE D VOLT AGE OUT PUT CONFIGURAT IONS
Figure 21 shows the AD768 configured to provide a unipolar
output range of approximately 0 V to –1 V. T he nominal full-
scale current of 20 mA flows through the parallel combination
of the 50
R
L
resistor and the 1 k
DAC output resistance
(from the R-2R ladder), for a combined 47.6
. T his produces
an ideal full-scale voltage of –0.952 V with respect to LADCOM.
In addition, the 1 k
DAC output resistance has a tolerance of
±
20% which may vary the full-scale gain by
±
1%. T his linear
variation results in a gain error which can be easily compensated
for by adjusting I
REFIN
.
1
27
28
VA
VB
AD768
R
49.9
R
49.9
IOUTA
LADCOM
IOUTB
Figure 21. 0 V to –1 V Unbuffered Voltage Output
In this configuration, it is important to note the restrictions from
the output compliance limits. T he maximum negative voltage
compliance is –1.2 V, prohibiting use of a 100
load to produce
a 0 V to –2 V output swing. One additional consideration for
operation in this mode is integral nonlinearity. As the voltage at
the output node changes, the finite output impedance of the
DAC current steering switches gives rise to small changes in the
output current that vary with output voltage, producing a bow
(up to 8 LSBs) in the INL. For optimal INL performance, the
buffered voltage output mode is recommended.
T he INL is also slightly dependent on the termination of the
unused output (IOUT B) as described in the ANALOG OUT -
PUT section. T o eliminate this effect, IOUT B should be termi-
nated with the same impedance as IOUT A, so both outputs see
the same resistive divider to ground. T his will keep the current
in LADCOM constant, minimizing any code-dependent IR
drops within the DAC ladder that may give rise to additional
nonlinearities.
AC-Coupled Output
Configuring the output as shown in Figure 22 provides a bipolar
output signal from the AD768 without requiring the use of a
summing amplifier. T he ac load impedance presented to the
DAC output is the parallel combination of the AD768’s output
impedance, R
L
, and bias resistor R
B
. T he nominal output swing
with the values given in Figure 22 is
±
0.5 V assuming R
B
>> R
L
.
T he gain of the circuit will be a function of the tolerances of the
impedances R
LAD
, R
B
, and R
L
.
Choosing the value of R
B
and C will depend primarily on the
desired –3 dB high pass cutoff frequency and the bias current,
I
B
, of the subsequent stage connected to R
B
. T he –3 dB fre-
quency can be approximated by the equation,
f
–3 dB
= 1/
[
2
×
π
×
(
R
B
+
R
L
i
R
LAD
)
×
C
].
T he dc offset of the output is a function of the bias current of
the subsequent stage and the value of R
B
. For example, if
C = 390 pF, R
B
= 20 k
, and I
B
= 1.0
μ
A, the –3 dB frequency
is approximately 20.4 kHz and the dc offset would be 20mV.
1
27
28
R
B
AD768
R
49.9
IOUTA
LADCOM
IOUTB
R
49.9
I
B
C
Figure 22. 0.5 V to –0.5 V Unbuffered AC-Coupled Output
BUFFE RE D VOLT AGE OUT PUT CONFIGURAT IONS
Unipolar Configuration
For positive output voltages, or voltage ranges greater than
allowed by output compliance limits, some type of external
buffer is needed. A wide variety of amplifiers may be selected
based on considerations such as speed, accuracy and cost. T he
AD9631 is an excellent choice when dynamic performance is
important, offering low distortion up to 10 MHz. Figure 23
shows the implementation of 0 V to +2 V full-scale unipolar
buffered voltage output. T he amplifier establishes a summing
node at ground for the DAC output. T he buffered output volt-
age results from the DAC output current flowing through the
amplifier’s feedback resistor, R
FB
. In this case, the 20 mA full-
scale current across R
FB
(100
) produces an output voltage
range of 0 V through +2 V. T he same configuration using a pre-
cision amplifier such as the AD845 is recommended for optimal
dc linearity.
1
27
28
AD768
R
FB
100
IOUTA
LADCOM
IOUTB
A1
Figure 23. Unipolar 0 V to +2 V Buffered Voltage Output
Buffered Output Using a Current Divider
T he configuration shown in Figure 23 may not be possible in
cases where the amplifier cannot supply the requisite 20mA
feedback current. As an alternative, Figure 24 shows amplifier
A1 in conjunction with a resistive current divider. T he values of
R
FF
and R
L
are chosen to limit the current, I
3
, which must be
supplied by A1. Current, I
2
, is shunted to ground through resis-
tor, R
L
. T he parallel combination of R
FF
and R
L
should not ex-
ceed 60
to avoid exceeding the specified compliance voltage.
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