t1 t3
參數(shù)資料
型號(hào)： AD7664ASTZRL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 8/24頁(yè)
文件大?。?/td> 0K
描述： IC ADC 16BIT UNIPOLAR 48LQFP
標(biāo)準(zhǔn)包裝： 2,000
系列： PulSAR®
位數(shù)： 16
采樣率（每秒）： 570k
數(shù)據(jù)接口： 串行，并聯(lián)
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 115mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類(lèi)型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 帶卷 (TR)
輸入數(shù)目和類(lèi)型： 2 個(gè)偽差分，單極
配用： EVAL-AD7664CBZ-ND - BOARD EVALUATION FOR AD7664
REV. E
–16–
AD7664
PREVIOUS
CONVERSION
t1
t3
t12
t13
t4
CS = 0
CNVST,
RD
BUSY
DATABUS
Figure 15. Slave Parallel Data Timing for Reading
(Read during Convert)
SERIAL INTERFACE
The AD7664 is configured to use the serial interface when the
SER/
PAR is held HIGH. The AD7664 outputs 16 bits of data,
MSB first, on the SDOUT pin. This data is synchronized with
the 16 clock pulses provided on the SCLK pin. The output data
is valid on both the rising and falling edge of the data clock.
MASTER SERIAL INTERFACE
Internal Clock
The AD7664 is configured to generate and provide the serial data
clock SCLK when the EXT/
INT pin is held LOW. The AD7664
also generates a SYNC signal to indicate to the host when the
serial data is valid. The serial clock SCLK and the SYNC signal
can be inverted, if desired. Depending on RDC/SDIN input,
the data can be read after each conversion or during the fol-
lowing conversion. Figures 16 and 17 show the detailed timing
diagrams of these two modes.
t3
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
t28
t29
t14
t18
t19
t20
t21
t24
t26
t27
t23
t22
t16
t15
12
3
14
15
16
D15
D14
D2
D1
D0
X
EXT/
INT = 0
RDC/SDIN = 0
INVSCLK = INVSYNC = 0
t25
t30
Figure 16. Master Serial Data Timing for Reading (Read after Convert)
EXT/
INT = 0
RDC/SDIN = 1
INVSCLK = INVSYNC = 0
t3
t1
t17
t14
t19
t20 t21
t24
t26
t25
t27
t23
t22
t16
t15
D15
D14
D2
D1
D0
X
12
3
14
15
16
t18
BUSY
CS, RD
CNVST
SYNC
SCLK
SDOUT
Figure 17. Master Serial Data Timing for Reading (Read Previous Conversion during Convert)
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