參數(shù)資料
型號: AD7625BCPZRL7
廠商: Analog Devices Inc
文件頁數(shù): 1/24頁
文件大?。?/td> 0K
描述: IC ADC 16BIT 6MSPS SAR 32LFCSP
設(shè)計資源: High Speed, Precision, Differential AC-Coupled Drive Circuit for AD7625 (CN0080)
標準包裝: 1,500
系列: PulSAR®
位數(shù): 16
采樣率(每秒): 6M
數(shù)據(jù)接口: 串行
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 190mW
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 32-LFCSP-VQ(5x5)
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 1 個差分,雙極
16-Bit, 6 MSPS, PulSAR
Differential ADC
Data Sheet
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevicesforitsuse,norforanyinfringementsofpatentsorother
rightsofthirdpartiesthatmayresultfromitsuse.Specificationssubjecttochangewithoutnotice.No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
2009–2012 Analog Devices, Inc. All rights reserved.
FEATURES
Throughput: 6 MSPS
SNR: 93 dB
INL: ±0.45 LSB typical, ±1 LSB maximum
DNL: ±0.3 LSB typical, ±0.5 LSB maximum
Power dissipation: 135 mW
32-lead LFCSP (5 mm × 5 mm)
SAR architecture
No latency/no pipeline delay
16-bit resolution with no missing codes
Zero error: ±1.5 LSB
Differential input voltage: ±4.096 V
Serial LVDS interface
Self-clocked mode
Echoed-clock mode
Can use LVDS or CMOS for conversion control (CNV signal)
Reference options
Internal: 4.096 V
External (1.2 V) buffered to 4.096 V
External: 4.096 V
APPLICATIONS
High dynamic range telecommunications
Receivers
Digital imaging systems
High speed data acquisition
Spectrum analysis
Test equipment
FUNCTIONAL BLOCK DIAGRAM
AD7625
CLOCK
LOGIC
SERIAL
LVDS
IN–
IN+
REFIN
REF VCM
SAR
÷2
CNV+, CNV–
VIO
D+, D–
DCO+, DCO–
CLK+, CLK–
1.2V
BAND GAP
CAP
DAC
07652-
001
Figure 1.
GENERAL DESCRIPTION
The AD7625 is a 16-bit, 6 MSPS, charge redistribution successive
approximation register (SAR) based architecture analog-to-digital
converter (ADC). SAR architecture allows unmatched perfor-
mance both in noise (93 dB SNR) and in linearity (1 LSB). The
AD7625 contains a high speed, 16-bit sampling ADC, an internal
conversion clock, and an internal buffered reference. On the
CNV± rising edge, it samples the voltage difference between the
IN+ and IN pins. The voltages on these pins swing in opposite
phase between 0 V and REF. The 4.096 V reference voltage, REF,
can be generated internally or applied externally.
All converted results are available on a single LVDS self-clocked
or echoed-clock serial interface, reducing external hardware
connections.
The AD7625 is housed in a 32-lead, 5 mm × 5 mm LFCSP with
operation specified from 40°C to +85°C.
Table 1. Fast PulSAR ADC Selection
Input Type
Resolution (Bits)
1 MSPS to <2 MSPS
2 MSPS to 3 MSPS
6 MSPS
Differential (Ground Sense)
16
16
16
16
True Bipolar
16
Differential (Antiphase)
16
AD7625
16
18
18
18
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