參數(shù)資料
型號(hào)： AD7612BSTZ-RL
廠商： ANALOG DEVICES INC
元件分類： ADC
英文描述： 16-Bit, 750 kSPS, Unipolar/Bipolar Programmable Input PulSAR ADC
中文描述： 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48
封裝： LEAD FREE, MS-026BBC, LQFP-48
文件頁(yè)數(shù)： 10/32頁(yè)
文件大?。?/td> 587K
代理商： AD7612BSTZ-RL
AD7612
Pin No.
24
Rev. 0 | Page 10 of 32
Mnemonic
D11 or
RDERROR
Type
1
DO
Description
In parallel mode, this output is used as Bit 11 of the parallel port data output bus.
Serial Data Read Error. In serial slave mode (SER/PAR = high, EXT/INT = high), this output is used as an
incomplete data read error flag. If a data read is started and not completed when the current
conversion is complete, the current data is lost and RDERROR is pulsed high.
In parallel mode, this output is used as Bit 12 of the parallel port data output bus.
Serial Configuration Hardware/Software Select. In serial mode, this input is used to configure
the AD7612 by hardware or software. See the Hardware Configuration section and Software
Configuration section.
When HW/SW = low, the AD7612 is configured through software using the serial configuration register.
When HW/SW = high, the AD7612 is configured through dedicated hardware input pins.
In parallel mode, this output is used as Bit 13 of the parallel port data output bus.
Serial Configuration Data Input. In serial software configuration mode (SER/PAR = high, HW/SW = low)
this input is used to serially write in, MSB first, the configuration data into the serial configuration
register. The data on this input is latched with SCCLK. See the Software Configuration section.
In parallel mode, this output is used as Bit 14 of the parallel port data output bus.
Serial Configuration Clock. In serial software configuration mode (SER/PAR = high, HW/SW = low) this
input is used to clock in the data on SCIN. The active edge where the data SCIN is updated depends on
the logic state of the INVSCLK pin. See the Software Configuration section.
In parallel mode, this output is used as Bit 15 of the parallel port data output bus.
Serial Configuration Chip Select. In serial software configuration mode (SER/PAR = high, HW/SW = low)
this input enables the serial configuration port. See the Software Configuration section.
Busy Output. Transitions high when a conversion is started, and remains high until the conversion
is complete and the data is latched into the on-chip shift register. The falling edge of BUSY can be
used as a data ready clock signal. Note that in master read after convert mode (SER/PAR = high,
EXT/INT = low, RDC = low) the busy time changes according to Table 4.
Input Range Select. Used in conjunction with BIPOLAR per the following:
Input Range
BIPOLAR
TEN
0 V to 5 V
Low
Low
0 V to 10 V
Low
High
±5 V
High
Low
±10 V
High
High
Read Data. When CS and RD are both low, the interface parallel or serial output bus is enabled.
Chip Select. When CS and RD are both low, the interface parallel or serial output bus is enabled. CS is
also used to gate the external clock in slave serial mode (not used for serial programmable port).
Reset Input. When high, reset the AD7612. Current conversion, if any, is aborted. The falling edge of
RESET resets the data outputs to all zero’s (with OB/2C = high) and clears the configuration register.
See the Digital Interface section. If not used, this pin can be tied to OGND.
Power-Down Input. When PD = high, power down the ADC. Power consumption is reduced and
conversions are inhibited after the current one is completed. The digital interface remains active
during power down.
Conversion Start. A falling edge on CNVST puts the internal sample-and-hold into the hold state and
initiates a conversion.
Input Range Select. See description for Pin 30.
Reference Input/Output.
When PDREF/PDBUF = low, the internal reference and buffer are enabled, producing 5 V on this pin.
When PDREF/PDBUF = high, the internal reference and buffer are disabled, allowing an externally
supplied voltage reference up to AVDD volts. Decoupling with at least a 22 μF is required with or
without the internal reference and buffer. See the Reference Decoupling section.
Reference Input Analog Ground. Connected to analog ground plane.
Analog Input Ground Sense. Should be connected to the analog ground plane or to a remote sense ground.
High Voltage Positive Supply. Normally +7 V to +15 V.
High Voltage Negative Supply. Normally 0 V to 15 V (0 V in unipolar ranges).
25
D12 or
HW/SW
DI/O
26
D13 or
SCIN
DI/O
27
D14 or
SCCLK
DI/O
28
D15 or
SCCS
DI/O
29
BUSY
DO
30
TEN
DI
2
31
32
RD
CS
DI
DI
33
RESET
DI
34
PD
DI
2
35
CNVST
DI
36
37
BIPOLAR
REF
DI
2
AI/O
38
39
40
41
REFGND
IN
VCC
VEE
AI
AI
P
P
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