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參數(shù)資料
| 型號(hào)： | AD760AQ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/12頁 |
| 文件大小： | 0K |
| 描述： | IC DAC 16BIT W/AMP SRL 28-CDIP |
| 產(chǎn)品培訓(xùn)模塊： | Data Converter Fundamentals DAC Architectures |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | DACPORT® |
| 設(shè)置時(shí)間： | 6µs |
| 位數(shù)： | 16 |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 雙 ± |
| 功率耗散（最大）： | 725mW |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 28-CDIP（0.600"，15.24mm） |
| 供應(yīng)商設(shè)備封裝： | 28-CDIP |
| 包裝： | 管件 |
| 輸出數(shù)目和類型： | 2 電壓，單極；2 電壓，雙極 |
| 采樣率（每秒）： | 167k |
| 產(chǎn)品目錄頁面： | 781 (CN2011-ZH PDF) |
–10–
AD760
REV. A
Byte Mode Operation
is enabled by setting SER high, which
configures DB0–DB7 as data inputs. In this mode HBE and
LBE
are used to identify the data as either the high byte or the
low byte of the 16-bit word. The user can load the data in either
order into the first rank latch using the rising edge of the CS
signal as shown in Figure 1a. The status of Pin 17 when CLR is
strobed determines whether the AD760 clears to unipolar or
bipolar zero. (But it cannot be hardwired to the desired state, as
in the serial mode.)
NOTE: CS is edge triggered. HBE, LBE, CLR, SER, CAL, and
LDAC are level triggered.
USING THE OUTPUT MULTIPLEXER
The onboard multiplexer allows the user to isolate the load from
the voltage variations at VOUT during calibration. To minimize
the glitch-impulse at MUXOUT, the multiplexer input, MUXIN,
should be tied to a voltage equal to the DAC’s negative
full-scale voltage. Since the DAC is loaded with the contents of
its first-rank latch before completing calibration, the DAC
should be programmed to negative full scale before calibrating.
This will minimize the voltage excursions of MUXOUT at the
beginning and end of calibration. If the glitch-impulse at the
beginning of calibration is not important, yet the user wants to
minimize the recovery time at MUXOUT, MUXIN should be set
to the voltage that corresponds to the data in the first-rank latch
before calibration is initiated.
The multiplexer series on-resistance limits its load-drive capability.
To attain 16-bit linearity, MUXOUT must be buffered with a
suitable op amp. The amplifier open loop-gain and common-
mode rejection contribute to gain error whereas the linearity of
these parameters affect the relative accuracy (or integral nonlin-
earity). In general, the amplifier linearity is not specified so its
effects must be determined empirically. Using the AD707, as
shown in Figure 9, the overall linearity error is within 0.5 LSB.
The AD707C/T initial voltage offset and its temperature coeffi-
cient will not contribute more than 0.1 LSB to the Bipolar Zero
Error over the entire operating temperature range. The settling
time to 1/2 LSB is typically 100 s for a 20 V step. For applica-
tions that require faster settling, the AD820 can be used to
attain full-scale settling to within a 1/2 LSB in 20 s. The addi-
tional linearity error from the AD820 will be no more than
0.25 LSB.
100pF
+VCC
0.1F
OUTPUT
AD707
OR
AD820
2
7
6
3
4
MUXOUT
22
23
28
27
1
4
MUXIN
AGND
VOUT
24
3
SPAN/
BIP OFF
CALOK
+VCC
1k
0.1F
AD760
–VEE
Figure 9. Buffering the AD760 Internal MUX
USING AN EXTERNAL MULTIPLEXER
An external multiplexer like the ADG419 allows the user to
minimize the glitch impulse when holding the output to any
predetermined voltage during calibration. The ADG419 can be
used with a high speed op amp like the AD829, as shown in Fig-
ure 10, to attain the fastest possible settling time while main-
taining 16-bit linearity. The settling time to 1/2 LSB for a 20 V
step is typically 10 s.
AD760 TO MC68HC11 (SPI* BUS) INTERFACE
The AD760 interface to the Motorola SPI (serial peripheral in-
terface) is shown in Figure 11. The MOSI, SCK, and SS pins of
the HC11 are respectively connected to the SIN, CS and LDAC
pins of the AD760. The majority of the interfacing issues are
taken care of in the software initialization. A typical routine such
as the one shown below begins by initializing the state of the
various SPI data and control registers.
The most significant data byte (MSBY) is then retrieved from
memory and processed by the SENDAT subroutine. The SS
pin is driven low by indexing into the PORTD data register and
clearing Bit 5. The MSBY is then sent to the SPI data
register where it is automatically transferred to the AD760.
*SPI is a registered trademark of Motorola.
MUXOUT
22
23
28
1
4
MUXIN
AGND
VOUT
24
3
SPAN/
BIP OFF
CALOK
+VCC
AD760
–VEE
1nF
+VCC
0.1F
OUT
2
7
6
3
4
1k
0.1F
–VEE
60pF
ADG419
8
2
1
6
27
5
4
+VCC
7
–VEE
AD829
Figure 10. Using the AD760 with an External MUX
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