參數(shù)資料
型號(hào)： AD7609BSTZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 5/36頁(yè)
文件大?。?/td> 0K
描述： IC DAS 18BIT 8CHANNEL 64-LQFP
特色產(chǎn)品： A/D Converters
標(biāo)準(zhǔn)包裝： 1
類型： 數(shù)據(jù)采集系統(tǒng)（DAS），ADC
分辨率（位）： 18 b
采樣率（每秒）： 200k
數(shù)據(jù)接口： DSP，MICROWIRE?，并聯(lián)，QSPI?，串行，SPI?
電壓電源： 模擬和數(shù)字
電源電壓： 2.3 V ~ 5 V，4.75 V ~ 5.25 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-LQFP
供應(yīng)商設(shè)備封裝： 64-LQFP（10x10）
包裝： 托盤
Data Sheet
AD7609
Rev. A | Page 13 of 36
Pin No.
Type1
Mnemonic
Description
8
DI
RANGE
Analog Input Range Selection. Logic input. The polarity on this pin determines the input range of the
analog input channels. If this pin is tied to a logic high, the analog input range is ±10 V for all
channels. If this pin is tied to a logic low, the analog input range is ±5 V for all channels. A logic
change on this pin has an immediate effect on the analog input range. Changing this pin during a
conversion is not recommended. See the Analog Input section for more details.
6
DI
PAR/
SER SEL
Parallel/Serial Interface Selection Input. Logic input. If this pin is tied to a logic low, the parallel
interface is selected. If this pin is tied to a logic high, the serial interface is selected.
In serial mode, the RD/SCLK pin functions as the serial clock input. The DB7/DOUTA and DB8/DOUTB pins
function as serial data outputs.
When the serial interface is selected, the DB[15:9] and DB[6:0] pins should be tied to AGND.
9, 10
DI
CONVST A,
CONVST B
Conversion Start Input A, Conversion Start Input B. Logic inputs. These logic inputs are used to initiate
conversions on the analog input channels. For simultaneous sampling of all input channels, CONVST A
and CONVST B can be shorted together and a single conversion start signal applied. Alternatively,
CONVST A can be used to initiate simultaneous sampling for V1, V2, V3, and V4, and CONVST B can be
used to initiate simultaneous sampling on the other analog inputs (V5, V6, V7, and V8). This is only
possible when oversampling is not switched on. When the CONVST A or CONVST B pin transitions
from low to high, the front-end track-and-hold circuitry for their respective analog inputs is set to
hold. This function allows a phase delay to be created inherently between the sets of analog inputs.
13
DI
CS
Chip Select. This active low logic input frames the data transfer. When both CS and RD are logic low in
parallel mode, the output bus (DB[15:0]) is enabled and the conversion result is output on the parallel
data bus lines. In serial mode, the CS is used to frame the serial read transfer and clocks out the MSB
of the serial output data.
12
DI
RD/SCLK
Parallel Data Read Control Input When Parallel Interface is Selected (RD)/Serial Clock Input When
Serial Interface is Selected (SCLK). When both CS and RD are logic low in parallel mode, the output
bus is enabled. In parallel mode, two RD pulses are required to read the full 18 bits of conversion
results from each channel. The first RD pulse outputs DB[17:2], and the second RD pulses outputs
DB[1:0]. In serial mode, this pin acts as the serial clock input for data transfers. The CS falling edge
takes the data output lines, DOUTA and DOUTB, out of three-state and clocks out the MSB of the
conversion result. The rising edge of SCLK clocks all subsequent data bits onto the serial data
outputs, DOUTA and DOUTB. For further information, see the Conversion Control section.
14
DO
BUSY
Busy Output. This pin transitions to a logic high after both CONVST A and CONVST B rising edges and
indicates that the conversion process has started. The BUSY output remains high until the conversion
process for all channels is complete. The falling edge of BUSY signals that the conversion data is being
latched into the output data registers and will be available to be read after a time, t4. Any data read
while BUSY is high should be complete before the falling edge of BUSY occurs. Rising edges on
CONVST A or CONVST B have no effect while the BUSY signal is high.
11
DI
RESET
Reset Input. When set to logic high, the rising edge of RESET resets the AD7609. The part must receive
a RESET pulse after power-up. To achieve the specified performance after the RESET signal, the tWAKE_UP
SHUTDOWN
time should elapse between power-on and the RESET pulse. The RESET high pulse should be
typically 100 ns wide. If a RESET pulse is applied during a conversion, the conversion is aborted. If a
RESET pulse is applied during a read, the contents of the output registers reset to all zeros.
15
DO
FRSTDATA
Digital Output. The FRSTDATA output signal indicates when the first channel, V1, is being read back
on either the parallel or serial interface. When the CS input is high, the FRSTDATA output pin is in
three-state. The falling edge of CS takes FRSTDATA out of three-state. In parallel mode, the falling
edge of RD corresponding to the result of V1 then sets the FRSTDATA pin high, indicating that the
result from V1 is available on the output data bus. The FRSTDATA output returns to a logic low
following the third falling edge of RD. In serial mode, FRSTDATA goes high on the falling edge of CS
as this clocks out the MSB of V1 on DOUTA. It returns low on the 18th SCLK falling edge after the CS
falling edge. See the Conversion Control section for more details.
7
DI
STBY
Standby Mode Input. This pin is used to place the AD7609 into one of two power-down modes:
standby mode or shutdown mode. The power-down mode entered depends on the state of the
RANGE pin, as shown in Table 8. When in standby mode, all circuitry except the on-chip reference,
regulators, and regulator buffers is powered down. When in shutdown mode, all circuitry is
powered down.
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