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參數(shù)資料
| 型號(hào)： | AD7609BSTZ-RL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DAS W/ADC 18BIT 8CH 64LQFP |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 類型： | 數(shù)據(jù)采集系統(tǒng)（DAS），ADC |
| 分辨率（位）： | 18 b |
| 采樣率（每秒）： | 200k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，并聯(lián)，QSPI?，串行，SPI? |
| 電壓電源： | 模擬和數(shù)字 |
| 電源電壓： | 2.3 V ~ 5 V，4.75 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（10x10） |
| 包裝： | 帶卷 (TR) |
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AD7609
Data Sheet
Rev. A | Page 12 of 36
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
AD7609
TOP VIEW
(Not to Scale)
64 63 62
61
60 59 58
57
V
1–
56 55 54 53 52 51 50 49
V
5+
V
4+
V
6+
V
3+
V
2+
V
1+
PIN 1
V
7+
V
8+
V
2–
V
3–
V
4–
V
5–
V
6–
V
7–
V
8–
DB13
DB12
DB11
DB14
V
DRI
V
E
DB1
17 18
19
20
21 22 23
24 25
AG
ND
26
27 28 29 30 31 32
DB2
DB3
DB4
DB5
DB6
DB7/
D
O
UT
A
DB9
DB10
DB8/
D
O
UT
B
AGND
AVCC 1
3
4
FRSTDATA
7
6
5
OS 2
2
8
9
10
12
13
14
15
16
11
DB0
BUSY
CONVST B
CONVST A
RANGE
RESET
RD/SCLK
CS
PAR/SER SEL
OS 1
OS 0
STBY
DECOUPLING CAPACITOR PIN
DATA OUTPUT
POWER SUPPLY
ANALOG INPUT
GROUND PIN
DIGITAL OUTPUT
DIGITAL INPUT
REFERENCE INPUT/OUTPUT
DB15
REFIN/REFOUT
48
46
45
42
43
44
47
41
40
39
37
36
35
34
33
38
AGND
AVCC
REFGND
REFCAPA
AGND
REFCAPB
REFGND
REGCAP
AVCC
REF SELECT
09760-
007
Figure 7. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
Type1
Mnemonic
Description
1, 37, 38, 48
P
AVCC
Analog Supply Voltage 4.75 V to 5.25 V. This supply voltage is applied to the internal front-end
amplifiers and to the ADC core. These supply pins should be decoupled to AGND.
2, 26, 35,
40, 41, 47
P
AGND
Analog Ground. This pin is the ground reference point for all analog circuitry on the AD7609. All
analog input signals and external reference signals should be referred to these pins. All six of these
AGND pins should connect to the AGND plane of a system.
23
P
VDRIVE
Logic Power Supply Input. The voltage (2.3 V to 5 V) supplied at this pin determines the operating
voltage of the interface. This pin is nominally at the same supply as the supply of the host interface
(that is, DSP, FPGA).
36, 39
P
REGCAP
Decoupling Capacitor Pins for Voltage Output from Internal Regulator. These output pins should be
decoupled separately to AGND using a 1 μF capacitor. The voltage on these output pins is in the
range of 2.5 V to 2.7 V.
49, 51, 53,
55, 57, 59,
61, 63
AI+
V1+ to V8+
Analog Input V1+ to Analog Input V8+. These pins are the positive terminal of the true differential
analog inputs. The analog input range of these channels is determined by the RANGE pin.
50, 52, 54,
56, 58, 60,
62, 64
AI
V1 to V8
Analog Input V1 to Analog Input V8. These are the negative terminals of the true differential
analog inputs. The analog input range of these channels is determined by the RANGE pin. The signal
on this pin should be 180° out of phase with the corresponding Vx+ pin.
42
REF
REFIN/
REFOUT
Reference Input/ Reference Output. The on-chip reference of 2.5 V is available on this pin for external
use if the REF SELECT pin is set to a logic high. Alternatively, the internal reference can be disabled by
setting the REF SELECT pin to a logic low and an external reference of 2.5 V can be applied to this
input. See the Internal/External Reference section. Decoupling is required on this pin for both the
internal or external reference options. A 10 F capacitor should be applied from this pin to ground
close to the REFGND pins.
34
DI
REF SELECT
Internal/External Reference Selection Input. Logic input. If this pin is set to logic high, the internal
reference is selected and is enabled. If this pin is set to logic low, the internal reference is disabled and
an external reference voltage must be applied to the REFIN/REFOUT pin.
44, 45
REF
REFCAPA,
REFCAPB
Reference Buffer Output Force/Sense Pins. These pins must be connected together and decoupled to
AGND using a low ESR 10 μF ceramic capacitor.
43, 46
REF
REFGND
Reference Ground Pins. These pins should be connected to AGND.
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