With fSCLK = 20 MHz and a throughp" />
參數(shù)資料
型號(hào)： AD7495BRZ-REEL7
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 25/25頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT SRL LP W/REF 8-SOIC
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 10.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-SOIC（0.154"，3.90mm 寬）
供應(yīng)商設(shè)備封裝： 8-SOIC
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 1 個(gè)單端，單極
AD7475/AD7495
Rev. B | Page 8 of 24
TIMING EXAMPLE 1
With fSCLK = 20 MHz and a throughput of 1 MSPS, the cycle
time is t2 + 12.5(1/fSCLK) + tACQ = 1 μs. With t2 = 10 ns min, tACQ
is 365 ns. The 365 ns satisfies the requirement of 300 ns for tACQ.
In Figure 3, tACQ comprises 2.5(1/fSCLK) + t8 + tQUIET, where t8 =
45 ns. This allows a value of 195 ns for tQUIET, satisfying the
minimum requirement of 100 ns.
TIMING EXAMPLE 2
With fSCLK = 5 MHz and a throughput of 315 KSPS, the cycle
time is t2 + 12.5(1/fSCLK) + tACQ = 3.174 μs. With t2 = 10 ns min,
tACQ is 664 ns. The 664 ns satisfies the requirement of 300 ns for
tACQ. In Figure 3, tACQ comprises 2.5(1/fSCLK) + t8 + tQUIET, where
t8 = 45 ns. This allows a value of 119 ns for tQUIET, satisfying the
minimum requirement of 100 ns. As in this example and with
other slower clock values, the signal may already be acquired
before the conversion is complete, but it is still necessary
to leave 100 ns minimum tQUIET between conversions. In
Example 2, the signal should be fully acquired at approximately
Point C in Figure 3.
SCLK
1
5
13
15
SDATA
FOUR LEADING ZEROS
THREE-STATE
t4
2
3
16
t5
t3
tQUIET
tCONVERT
t2
THREE-STATE
DB11
DB10
DB2
DB0
t6
t7
t8
14
0
B
DB1
01684-B
-002
CS
4
Figure 2. Serial Interface Timing Diagram
SCLK
1
5
13
15
2
3
16
t5
tQUIET
tCONVERT
t2
t6
t8
14
B
45ns
tACQUISITION
12.5 (1/fSCLK)
10ns
1/THROUGHPUT
C
01684-B
-003
CS
4
Figure 3. Serial Interface Timing Example
200
μA
IOL
200
μA
IOH
CL
50pF
TO OUTPUT
PIN
1.6V
01684-B
-004
Figure 4. Load Circuit for Digital Output Timing Specifications
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