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| 型號： | AD7490BRU-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 14/29頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT 16CH 28-TSSOP T/R |
| 產(chǎn)品變化通告： | IDD Specification Change 17/Jun/2009 Product Discontinuance 27/Oct/2011 |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 12.5mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 16 個單端，單極 |
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AD7490
Data Sheet
Rev. D | Page 20 of 28
Auto Shutdown (PM1 = 0, PM0 = 1)
In this mode, the AD7490 automatically enters shutdown at the
end of each conversion when the control register is updated.
When the part is in shutdown, the track-and-hold is in hold
mode. Figure 24 shows the general diagram of the operation of
the AD7490 in this mode.
In shutdown mode, all internal circuitry on the AD7490 is
powered down. The part retains information in the control
register during shutdown. The AD7490 remains in shutdown
until the next CS falling edge it receives. On this CS falling edge,
the track-and-hold that was on hold while the part was in shut-
down mode returns to track-and-hold. Wake-up time from auto
shutdown is 1 μs, and the user should ensure that 1 μs elapses
before attempting a valid conversion. When running the AD7490
with a 20 MHz clock, one dummy cycle of 16 × SCLK should be
sufficient to ensure the part is fully powered up. During this
dummy cycle, the contents of the control register should remain
unchanged; therefore, the WRITE bit should be 0 on the DIN
line. This dummy cycle effectively halves the throughput rate of
the part, with every other conversion result being valid. In this
mode, the power consumption of the part is greatly reduced
with the part entering shutdown at the end of each conversion.
When the control register is programmed to move into auto
shutdown, it does so at the end of the conversion. The user can
move the ADC in and out of the low power state by controlling
the CS signal.
Auto Standby (PM1 = PM0 = 0)
In this mode, the AD7490 automatically enters standby mode at
the end of each conversion when the control register is updated.
Figure 25 shows the general diagram of the operation of the
AD7490 in this mode. When the part is in standby, portions of
the AD7490 are powered-down, but the on-chip bias generator
remains powered up. The part retains information in the control
register during standby. The AD7490 remains in standby until it
receives the next CS falling edge. On this CS falling edge, the
track-and-hold that was on hold while the part was in standby
returns to track. Wake-up time from standby is 1 μs; the user
should ensure that 1 μs elapses before attempting a valid conver-
sion on the part in this mode. When running the AD7490 with
a 20 MHz clock, one dummy cycle of 16 × SCLK should be
sufficient to ensure the part is fully powered up. During this
dummy cycle, the contents of the control register should remain
unchanged; therefore, the WRITE bit should be set to 0 on the
DIN line. This dummy cycle effectively halves the throughput
rate of the part with every other conversion result being valid.
In this mode, the power consumption of the part is greatly
reduced with the part entering standby at the end of each con-
version. When the control register is programmed to move into
auto standby, it does so at the end of the conversion. The user
can move the ADC in and out of the low power state by
controlling the CS signal.
0
269
1-
0
23
SCLK
116
DOUT
DIN
CS
DUMMY CONVERSION
CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCKS, PM1 = 0, PM0 = 1
CONTROL REGISTER CONTENTS SHOULD
NOT CHANGE, WRITE BIT = 0
PART ENTERS
SHUTDOWN ON CS
RISING EDGE AS
PM1 = 0, PM0 = 1
PART IS FULLY
POWERED UP
TO KEEP PART IN THIS MODE, LOAD PM1 = 0, PM0 = 1
IN CONTROL REGISTER OR SET WRITE BIT = 0
CHANNE L IDENTIFIER BITS + CONVERSION RESULT
DATA IN TO CONTROL/SHADOW REGISTER
CHANNE L IDENTIFIER BITS + CONVERSION RESULT
DATA IN TO CONTROL/SHADOW REGISTER
INVALID DATA
PART ENTERS
SHUTDOWN ON CS
RISING EDGE AS
PM1 = 0, PM0 = 1
PART BEGINS
TO POWER
UP ON CS
FALLING EDGE
Figure 24. Auto Shutdown Mode Operation
02
691
-02
4
SCLK
112
16
1
12
16
1
12
16
DOUT
DIN
CS
DUMMY CONVERSION
CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCKS, PM1 = 0, PM0 = 0
CONTROL REGISTER CONTENTS SHOULD
REMAIN UNCHANGED, WRITE BIT = 0
PART IS FULLY
POWERED UP
TO KEEP PART IN THIS MODE, LOAD PM1 = 0,
PM0 = 0 IN CONTROL REGISTER
PART ENTERS
STANDBY ON CS
RISING EDGE AS
PM1 = 0, PM0 = 0
PART ENTERS
STANDBY ON CS
RISING EDGE AS
PM1 = 0, PM0 = 0
PART BEGINS
TO POWER
UP ON CS
FALLING EDGE
CHANNE L IDENTIFIER BITS + CONVERSION RESULT
INVALID DATA
DATA IN TO CONTROL/SHADOW REGISTER
Figure 25. Auto Standby Mode Operation
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