參數(shù)資料
型號(hào)： AD7490BRU-REEL
廠商： Analog Devices Inc
文件頁數(shù)： 13/29頁
文件大小： 0K
描述： IC ADC 12BIT 16CH 28-TSSOP T/R
產(chǎn)品變化通告： IDD Specification Change 17/Jun/2009
Product Discontinuance 27/Oct/2011
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 12.5mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 16 個(gè)單端，單極
Data Sheet
AD7490
Rev. D | Page 19 of 28
Reference Section
An external reference source should be used to supply the 2.5 V
reference to the AD7490. Errors in the reference source result
in gain errors in the AD7490 transfer function and add to the
specified full-scale errors of the part. A capacitor of at least 0.1 μF
should be placed on the REFIN pin. Suitable reference sources
for the AD7490 include the AD780, REF192, AD1582, ADR03,
ADR381, ADR391, and ADR421.
If 2.5 V is applied to the REFIN pin, the analog input range can
either be 0 V to 2.5 V or 0 V to 5 V, depending on the RANGE
bit in the control register.
MODES OF OPERATION
The AD7490 has a number of different modes of operation.
These modes are designed to provide flexible power manage-
ment options. These options can be chosen to optimize the
power dissipation/throughput rate ratio for differing application
requirements. The mode of operation of the AD7490 is controlled
by the power management bits, PM1 and PM0, in the control
register, as detailed in Table 7. When power supplies are first
applied to the AD7490, care should be taken to ensure that the
part is placed in the required mode of operation (see the
Normal Mode (PM1 = PM0 = 1)
This mode is intended for the fastest throughput rate performance
because the user does not have to worry about any power-up
times with the AD7490 remaining fully powered at all times.
Figure 22 shows the general diagram of the operation of the
AD7490 in this mode.
02
69
1-
0
21
NOTES
1. CONTROL REGISTER DATA IS LOADED ON FIRST 12 SCLK CYCLES
2. SHADOW REGISTER DATA IS LOADED ON FIRST 16 SCLK CYCLES
CS
SCLK
116
12
CHANNE L IDENTIFIER BITS + CONVERSION RESULT
DATA IN TO CONTROL/SHADOW REGISTER
DOUT
DIN
Figure 22. Normal Mode Operation
The conversion is initiated on the falling edge of CS, and the
track-and-hold enters hold mode, as described in the Serial
Interface section. The data presented to the AD7490 on the
DIN line during the first 12 clock cycles of the data transfer is
loaded
to the control register (provided the WRITE bit is 1). If data is
to be written to the Shadow register (SEQ = 0, SHADOW = 1
on previous write), data presented on the DIN line during the
first 16 SCLK cycles is loaded into the Shadow register. The part
remains fully powered up in normal mode at the end of the
conversion as long as PM1 and PM0 are set to 1 in the write
transfer during that conversion. To ensure continued operation
in normal mode, PM1 and PM0 are both loaded with 1 on every
data transfer. Sixteen serial clock cycles are required to complete
the conversion and access the conversion result. The track-and-
hold goes back into track on the 14th SCLK falling edge. CS may
then idle high until the next conversion or may idle low until
sometime prior to the next conversion, (effectively idling CS low).
Once a data transfer is complete (DOUT has returned to three-
state WEAK/TRI bit = 0), another conversion can be initiated
after the quiet time, tQUIET, has elapsed by bringing CS low again.
Full Shutdown (PM1 = 1, PM0 = 0)
In this mode, all internal circuitry on the AD7490 is powered
down. The part retains information in the control register
during full shutdown. The AD7490 remains in full shutdown
until the power management bits in the control register, PM1
and PM0, are changed.
If a write to the control register occurs while the part is in
full shutdown, with the power management bits changed to
PM0 = PM1 = 1 (normal mode), the part begins to power up
on the CS rising edge. The track-and-hold that was in hold
while the part was in full shutdown returns to track on the 14th
SCLK falling edge.
To ensure that the part is fully powered up, tPOWER UP (t12) should
elapse before the next CS falling edge. Figure 23 shows the
general diagram for this mode.
02
69
1-
B
-02
2
SCLK
116
1
14
16
14
DOUT
PART IS IN FULL
SHUTDOWN
PART BEGINS TO POWER UP ON CS
RISING EDGE AS PM1 = 1, PM0 = 1
PART IS FULLY POWERED UP
ONCE
tPOWER UP HAS ELAPSED
DIN
CS
t12
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA IN TO CONTROL REGISTER
CONTROL REGISTER IS LOADED ON THE
FIRST 12 CLOCKS, PM1 = 1, PM0 = 1
TO KEEP PART IN NORMAL MODE, LOAD
PM1 = 1, PM0 = 1 IN CONTROL REGISTER
DATA IN TO CONTROL/SHADOW REGISTER
Figure 23. Full Shutdown Mode Operation
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