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參數(shù)資料
| 型號： | AD7466 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| 中文描述： | 1.8伏，微功耗，8/10/12-Bit在ADC的6引腳SOT - 23 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 171K |
| 代理商： | AD7466 |
AD7466/AD7467/AD7468
–13–
REV. PrC
MICROPROCESSOR INTERFACING
The serial interface on the AD7466/AD7467/AD7468
allows the part to be directly connected to a range of many
different microprocessors. This section explains how to
interface the AD7466/AD7467/AD7468 with some of the
more common microcontroller and DSP serial interface
protocols.
AD7466/7/8 to TMS320C5xC54x
The serial interface on the TMS320C5x uses a continuous
serial clock and frame synchronization signals to synchro-
nize the data transfer operations with peripheral devices
like the AD7466/67/68. The
CS input allows easy inter-
facing between the TMS320C5x and the AD7466/67/68
without any glue logic required. The serial port of the
TMS320C5x/C54x is set up to operate in burst mode
with internal CLKX (TX serial clock) and FSX (TX
frame sync). The serial port control register (SPC) must
have the following setup: FO = 0, FSM = 1, MCM = 1
and TXM = 1. The format bit, FO, may be set to 1 to set
the word length to 8-bits, in order to implement the
power-down mode on the AD7466/67/68.
The connection diagram is shown in Figure 18. It should
be noted that for signal processing applications, it is im-
perative that the frame synchronisation signal from the
TMS320C5x/C54x will provide equidistant sampling.
AD7466/7/8 to ADSP21xx
The ADSP21xx family of DSPs are interfaced directly to
the AD7466/67/68 without any glue logic required. The
SPORT control register should be set up as follows:
TFSW = RFSW = 1, Alternate Framing
INVRFS = INVTFS = 1, Active Low Frame Signal
DTYPE = 00, Right Justify Data
SLEN = 1111, 16-Bit Data words
ISCLK = 1, Internal serial clock
TFSR = RFSR = 1, Frame every word
IRFS = 0,
ITFS = 1.
The connection diagram is shown in Figure 19. The
ADSP21xx has the TFS and RFS of the SPORT tied
together, with TFS set as an output and RFS set as an
input. The DSP operates in Alternate Framing Mode and
the SPORT control register is set up as described. The
Frame synchronisation signal generated on the TFS is
tied to
CS and as with all signal processing applications
Figure 18. Interfacing to the TMS320C5x
equidistant sampling is necessary. However, in this ex-
ample, the timer interrupt is used to control the sampling
rate of the ADC and under certain conditions, equidistant
sampling may not be acheived.
The Timer registers etc. are loaded with a value
which will provide an interrupt at the required sample
interval. When an interrupt is received, a value is trans-
mitted with TFS/DT (ADC control word). The TFS is
used to control the RFS and hence the reading of data.
The frequency of the serial clock is set in the SCLKDIV
register. When the instrustion to transmit with TFS is
given, (i.e. AX0=TX0), the state of the SCLK is checked.
The DSP will wait until the SCLK has gone High, Low
and High before transmission will start. If the timer and
SCLK values are chosen such that the instruction to trans-
mit occurs on or near the rising edge of SCLK, then the
data may be transmitted or it may wait until the next clock
edge.
For example, the ADSP2111 has a master clock frequency
of 16MHz. If the SCLKDIV register is loaded with the
value 3 then a SCLK of 2MHz is obtained, and 8 master
clock periods will elapse for every 1 SCLK period. If the
timer registers are loaded with the value 803, then 100.5
SCLKs will occur between interrupts and subsequently
between transmit instructions. This situation will result in
non-equidistant sampling as the transmit instruction is
occuring on a SCLK edge. If the number of SCLKs be-
tween interrupts is a whole integer figure of N then equi-
distant sampling will be implemented by the DSP.
AD7466/67/68 to DSP56xxx
The connection diagram in figure 20 shows how the
AD7466/67/68 can be connected to the SSI (Synchronous
Serial Interface) of the DSP56xxx family of DSPs from
Motorola. The SSI is operated in Synchronous Mode
(SYN bit in CRB =1)
with internally generated 1-bit
clock period frame sync for both TX and RX (bits FSL1
=1 and FSL0 =0
in CRB). Set the word length to 16 by
setting bits WL1 =1 and WL0 = 0 in CRA. It should be
noted that for signal processing applications, it is impera-
tive that the frame synchronisation signal from the
DSP56xxx will provide equidistant sampling.
Figure 19. Interfacing to the ADSP-21xx
AD7466/7/8*
SDATA
SCLK
CS
TMS320C5x/C54x*
*Additional Pins omitted for clarity
CLKX
CLKR
DR
FSX
FSR
AD7466/7/8*
SCLK
CS
ADSP21xx*
*Additional Pins omitted for clarity
SCLK
DR
RFS
TFS
SDATA
pecifications
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