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參數(shù)資料
| 型號： | AD7466 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23 |
| 中文描述： | 1.8伏，微功耗，8/10/12-Bit在ADC的6引腳SOT - 23 |
| 文件頁數(shù)： | 11/15頁 |
| 文件大?。?/td> | 171K |
| 代理商： | AD7466 |
AD7466/AD7467/AD7468
–5–
REV. PrC
Parameter
AD7466
Units
Description
fSCLK
2
10
kHz min
T B D
MHz max
tCONVERT
16* tSCLK
tquiet
T B D
ns min
Minimum Quiet Time required between Bus Relinquish
and start of next conversion
t1
T B D
ns min
Minimum
CS Pulse Width
t2
10
ns min
CS to SCLK Setup Time
t3
3
T B D
ns max
Delay from
CS Until SDATA 3-State Disabled
t4
3
T B D
ns max
Data Access Time After SCLK Falling Edge
t5
0.4tSCLK
ns min
SCLK Low Pulse Width
t6
0.4tSCLK
ns min
SCLK High Pulse Width
t7
T B D
ns min
SCLK to Data Valid Hold Time
t8
4
T B D
ns max
SCLK falling Edge to SDATA High Impedance
tpower-up
5
TBD
s typ
Power up time from Full Power-down.
TIMINGSPECIFICATIONS1
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage level of 1.6 Volts.
2Mark/Space ratio for the SCLK input is 40/60 to 60/40.
3Measured with the load circuit of Figure 1 and defined as the time required for the output to cross 0.8 V or 2.0 V.
4t
8 is derived form the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to
remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the
part and is independent of the bus loading.
5See Power-up Time section.
Specifications subject to change without notice.
(VDD = +1.8 V to +3.6 V; TA = TMIN to TMAX, unless otherwise noted.)
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD7466/AD7467/AD7468 feature proprietary ESD protection circuitry, per-
manent damage may occur on devices subjected to high energy electrostatic discharges. There-
fore, proper ESD precautions are recommended to avoid performance degradation or loss of
functionality.
ABSOLUTE MAXIMUM RATINGS
1
(TA = +25°C unless otherwise noted)
VDD to GND
–0.3 V to TBD V
Analog Input Voltage to GND
–0.3 V to VDD + 0.3 V
Digital Input Voltage to GND
–0.3 V to TBDV
Digital Output Voltage to GND
–0.3 V to VDD + 0.3 V
Input Current to Any Pin Except Supplies
2
±10 mA
Operating Temperature Range
Commercial (A, B Version)
–40°C to +85°C
Storage Temperature Range
–65°C to +150°C
Junction Temperature
+150°C
SOT-23 Package, Power Dissipation
450 mW
θ
JA Thermal Impedance
229.6°C/W (SOT23)
205.9°C/W (SOIC)
θ
JC Thermal Impedance
91.99°C/W (SOT23)
43.74°C/W (SOIC)
Lead Temperature, Soldering
Vapor Phase (60 secs)
+215°C
Infared (15 secs)
+220°C
ESD
T B D
NOTES
1Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch up.
Figure 1. Load Circuit for Digital Output Timing
Specifications
+1.6V
IOL
200 A
IOH
TO
OUT P UT
PIN
C L
50p F
pecifications
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