參數(shù)資料
型號(hào)： AD7457BRT-REEL7
廠(chǎng)商： ANALOG DEVICES INC
元件分類(lèi)： ADC
英文描述： Low Power, Pseudo Differential, 100 kSPS 12-Bit ADC in an 8-Lead SOT-23
中文描述： 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝： MO-178BA, SOT-23, 8 PIN
文件頁(yè)數(shù)： 6/20頁(yè)
文件大?。?/td> 532K
代理商： AD7457BRT-REEL7
AD7457
Rev. A | Page 14 of 20
In applications with a slow SCLK, it is possible to read in data
on each SCLK rising edge. In this case, the first falling edge of
SCLK after the CS rising edge clocks out the second leading
zero and can be read in on the following rising edge. If the first
SCLK edge after the CS rising edge is a falling edge, the first
leading zero that was clocked out when CS went high is missed,
unless it was not read on the first SCLK falling edge. The fif-
teenth falling edge of SCLK clocks out the last bit of data, which
can be read in by the following rising SCLK edge.
POWER CONSUMPTION
The AD7457 automatically enters power-down at the end of
each conversion. When in the power-down mode, all analog
circuitry is powered down and the current consumption is 1 A.
To achieve the specified power consumption (which is the
lowest), there are a few things the user should keep in mind.
The conversion time of the device is determined by the serial
clock frequency. The faster the SCLK frequency, the shorter the
conversion time. Therefore, as the clock frequency used is
increased, the ADC is dissipating power for a shorter period of
time (during conversion) and it remains in power-down for a
longer percentage of the cycle time or throughput rate. This
can be seen in Figure 23, which shows typical IDD vs. SCLK
frequency for VDD of 3 V and 5 V, when operating the device at
the maximum throughput of 100 kSPS.
SCLK Frequency (MHz)
I DD
(mA)
2.5
2.0
1.0
1.5
0.5
0
02
8
6
410
VDD = 3V
VDD = 5V
03157-0-023
TA = 25°C
Figure 23. IDD vs. SCLK Frequency for VDD = 3 V and 5 V
when Operating at 100 kSPS
Figure 24 shows typical power consumption vs. throughput rate
for the maximum SCLK frequency of 10 MHz. In this case, the
conversion time is the same for all throughputs, because the
SCLK frequency is fixed. As the throughput rate decreases, the
average power consumption decreases, because the ADC spends
more time in power-down.
020
THROUGHPUT (kSPS)
POWER
(
m
W)
VDD = 3V
VDD = 5V
03157-0-024
40
60
80
100
0
2.5
2.0
1.5
1.0
0.5
TA = 25°C
Figure 24. Power vs. Throughput Rate for SCLK = 10 MHz for VDD = 3 V and 5 V
MICROPROCESSOR INTERFACING
The serial interface of the AD7457 allows the part to be con-
nected to a range of different microprocessors. This section
explains how to interface the AD7457 with the ADSP-218x
serial interface.
AD7457 to ADSP-218x
The ADSP-218x family of DSPs can be interfaced directly to the
AD7457 without any glue logic. The serial clock for the ADC is
provided by the DSP. SDATA from the ADC is connected to the
data receive (DR) input of the serial port and CS can be con-
trolled by a flag (FL0). The connection diagram is shown in
SCLK
SDATA
CS
SCLK
DR0
RFS
FL0
1ADDITIONAL PINS OMITTED FOR CLARITY.
SPORT0
SPORT1
AD74571
ADSP-21xx1
03157-0-025
Figure 25. AD7457 to ADSP-218x
SPORT0 must be enabled to receive the conversion data and to
provide the SCLK, while SPORT1 must be configured for flags
and so on.
相關(guān)PDF資料
PDF描述
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AD7466BRT 1.8 V, Micro-Power, 8/10/12-Bit ADCs in 6 Lead SOT-23
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