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參數(shù)資料
| 型號： | AD7453ARTZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/21頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT DFF 600KSPS SOT23-8 |
| 設(shè)計(jì)資源： | Measuring -48 V High-Side Current Using AD629, AD8603, AD780, and AD7453 (CN0100) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 555k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 7.25mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | SOT-23-8 |
| 供應(yīng)商設(shè)備封裝： | SOT-23-8 |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類型： | 1 個(gè)偽差分，單極 |
| 其它名稱： | AD7453ARTZ-REEL7DKR |
AD7453
Rev. B | Page 5 of 20
TIMING SPECIFICATIONS
Guaranteed by characterization. All input signals are specified with tr = tf = 5 ns (10% to 90% of VDD) and timed from a voltage
level of 1.6 V.
See Figure 2 and the Serial Interface section.
VDD = 2.7 V to 5.25 V, fSCLK = 10 MHz, fS = 555 kSPS, VREF = 2.5 V, TA = TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter
Limit at TMIN, TMAX
Unit
Description
10
kHz min
10
MHz max
tCONVERT
16 × tSCLK
tSCLK = 1/fSCLK
1.6
s max
tQUIET
60
ns min
Minimum quiet time between the end of a serial read and the next falling edge of CS
t1
10
ns min
Minimum CS pulse width
t2
10
ns min
CS falling edge to SCLK falling edge setup time
t32
20
ns max
Delay from CS falling edge until SDATA three-state disabled
t42
40
ns max
Data access time after SCLK falling edge
t5
0.4 tSCLK
ns min
SCLK high pulse width
t6
0.4 tSCLK
ns min
SCLK low pulse width
t7
10
ns min
SCLK edge to data valid hold time
t83
10
ns min
SCLK falling edge to SDATA three-state enabled
35
ns max
SCLK falling edge to SDATA three-state enabled
tPOWER-UP 4
1
s max
Power-up time from full power-down
t3
t2
t4
t7
t8
t6
t1
t5
tQUIET
tCONVERT
CS
SCLK
SDATA
4 LEADING ZEROS
THREE-STATE
12
3
4
5
13
14
15
16
0
DB11
DB10
DB2
DB1
DB0
B
03155-A
-002
Figure 2. AD7453 Serial Interface Timing Diagram
1 Mark/space ratio for the SCLK input is 40/60 to 60/40.
2 Measured with the load circuit of
and defined as the time required for the output to cross 0.8 V or 2.4 V with V
Figure 3
Figure 3.
DD
= 5 V, and the time required for an output to
cross 0.4 V or 2.0 V for VDD = 3 V.
3 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of
The measured number is then extrapolated
back to remove the effects of charging or discharging the 25 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
4 See Power-Up Time section.
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