參數(shù)資料
型號： AD7440BRMZ
廠商： Analog Devices Inc
文件頁數(shù)： 25/29頁
文件大?。?/td> 0K
描述： IC ADC 10BIT DIFF IN 1MSPS 8MSOP
標(biāo)準(zhǔn)包裝： 50
位數(shù)： 10
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 9.25mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)差分，單極
AD7440/AD7450A
Rev. C | Page 4 of 28
Parameter
Test Conditions/Comments
B Version
Unit
CONVERSION RATE
Conversion Time
888 ns with an 18 MHz SCLK
16
SCLK cycles
Track-and-Hold Acquisition Time2
Sine wave input
200
ns max
Step input
290
ns max
Throughput Rate
1
MSPS max
POWER REQUIREMENTS
VDD
Range: 3 V + 20%/–10%; 5 V ± 5%
2.7/5.25
V min/V max
Normal Mode (Static)
SCLK on or off
0.5
mA typ
Normal Mode (Operational)
VDD = 4.75 V to 5.25 V
1.95
mA max
VDD = 2.7 V to 3.6 V
1.45
mA max
Full Power-Down Mode
SCLK on or off
1
μA max
Power Dissipation
Normal Mode (Operational)
VDD = 5 V, 1.55 mW typ for 100 kSPS9
9.25
mW max
VDD = 3 V, 0.6 mW typ for 100 kSPS9
4
mW max
Full Power-Down Mode
VDD = 5 V, SCLK on or off
5
μW max
VDD = 3 V, SCLK on or off
3
μW max
1 Common-mode voltage. The input signal can be centered on a dc common-mode voltage in the range specified in Figure 28 and Figure 29.
2 See the Terminology section.
3 Analog inputs with slew rates exceeding 27 V/μs (full-scale input sine wave > 3.5 MHz) within the acquisition time can cause the converter to return an
incorrect result.
4 Because the input spans of VIN+ and VIN– are both VREF and are 180° out of phase, the differential voltage is 2 × VREF.
5 The AD7440 is functional with a reference input from 100 mV and for VDD = 5 V; the reference can range up to 3.5 V.
6 The AD7440 is functional with a reference input from 100 mV and for VDD = 3 V; the reference can range up to 2.2 V.
7 Guaranteed by characterization.
8 Measured with a midscale dc input.
9 See the Power vs. Throughput section.
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AD7440BRTR2 制造商:AD 功能描述:New
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