VREF
參數(shù)資料
型號(hào)： AD7440BRMZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 2/29頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT DIFF IN 1MSPS 8MSOP
標(biāo)準(zhǔn)包裝： 50
位數(shù)： 10
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 9.25mW
電壓電源： 單電源
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 8-TSSOP，8-MSOP（0.118"，3.00mm 寬）
供應(yīng)商設(shè)備封裝： 8-MSOP
包裝： 管件
輸入數(shù)目和類型： 1 個(gè)差分，單極
AD7440/AD7450A
Rev. C | Page 9 of 28
PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS
03051-A
-005
VREF
VIN+
VIN–
GND
8
7
6
5
VDD 1
SCLK
2
SDATA
3
CS
4
AD7440/
AD7450A
TOP VIEW
(Not to Scale)
Figure 5. Pin Configuration for 8-Lead SOT-23
03051-A
-006
VDD
SCLK
SDATA
CS
8
7
6
5
VREF 1
VIN+ 2
VIN– 3
GND 4
AD7440/
AD7450A
TOP VIEW
(Not to Scale)
Figure 6. Pin Configuration for 8-Lead MSOP
Table 5. Pin Function Descriptions
Mnemonic
Function
VREF
Reference Input for the AD7440/AD7450A. An external reference must be applied to this input. For a 5 V power supply, the
reference is 2.5 V (±1%) for specified performance. For a 3 V power supply, the reference is 2 V (±1%) for specified
performance. This pin should be decoupled to GND with a capacitor of at least 0.1 μF. See the Reference section for more
details.
VIN+
Positive Terminal for Differential Analog Input.
VIN–
Negative Terminal for Differential Analog Input.
GND
Analog Ground. Ground reference point for all circuitry on the AD7440/AD7450A. All analog input signals and any external
reference signal should be referred to this GND voltage.
CS
Chip Select. Active low logic input. This input provides the dual function of initiating a conversion on the AD7440/AD7450A
and framing the serial data transfer.
SDATA
Serial Data. Logic output. The conversion result from the AD7440/AD7450A is provided on this output as a serial data stream.
The bits are clocked out on the falling edge of the SCLK input. The data stream of the AD7450A consists of four leading zeros
followed by the 12 bits of conversion data, which are provided MSB first; the data stream of the AD7440 consists of four
leading zeros, followed by the 10 bits of conversion data, followed by two trailing zeros. In both cases, the output coding is
twos complement.
SCLK
Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the
clock source for the conversion process.
VDD
Power Supply Input. VDD is 3 V (+20%/–10%) or 5 V (±5%). This supply should be decoupled to GND with a 0.1 μF capacitor and
a 10 μF tantalum capacitor in parallel.
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相關(guān)代理商/技術(shù)參數(shù)
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AD7440BRTR2 制造商:AD 功能描述:New
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