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參數(shù)資料
| 型號： | AD7400YRWZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MODULATOR SIGMA-DELTA 16-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 調(diào)制器 |
| 分辨率（位）： | 16 b |
| 采樣率（每秒）： | 10M |
| 數(shù)據(jù)接口： | 串行 |
| 電壓電源： | 單電源 |
| 電源電壓： | 4.5 V ~ 5.25 V |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
Data Sheet
AD7400
Rev. G | Page 15 of 20
DIGITAL FILTER
A Sinc3 filter is recommended for use with the AD7400. This
filter can be implemented on an FPGA or a DSP. The following
Verilog code provides an example of a Sinc3 filter implementation
on a Xilinx Spartan-II 2.5 V FPGA. This code can possibly be
compiled for another FPGA, such as an Altera device. Note
that the data is read on the negative clock edge in this case,
although it can be read on the positive edge if preferred. Figure 28
shows the effect of using different decimation rates with various
filter types.
/*`Data is read on negative clk edge*/
module DEC256SINC24B(mdata1, mclk1, reset,
DATA);
input
mclk1;
/*used to clk filter*/
input
reset;
/*used to reset filter*/
input
mdata1;
/*ip data to be
filtered*/
output [15:0] DATA;
/*filtered op*/
integer location;
integer info_file;
reg [23:0]
ip_data1;
reg [23:0]
acc1;
reg [23:0]
acc2;
reg [23:0]
acc3;
reg [23:0]
acc3_d1;
reg [23:0]
acc3_d2;
reg [23:0]
diff1;
reg [23:0]
diff2;
reg [23:0]
diff3;
reg [23:0]
diff1_d;
reg [23:0]
diff2_d;
reg [15:0]
DATA;
reg [7:0]
word_count;
reg word_clk;
reg init;
/*Perform the Sinc ACTION*/
always @ (mdata1)
if(mdata1==0)
ip_data1 <= 0;
/* change from a 0
to a -1 for 2's comp */
else
ip_data1 <= 1;
/*ACCUMULATOR (INTEGRATOR)
Perform the accumulation (IIR) at the speed
of the modulator.
04718-021
MCLKOUT
IP_DATA1
ACC1+
ACC2+
ACC3
+
Z
+
Z
+
Z
Figure 25. Accumulator
Z = one sample delay
MCLKOUT = modulators conversion bit rate
*/
always @ (negedge mclk1 or posedge reset)
if (reset)
begin
/*initialize acc registers on reset*/
acc1 <= 0;
acc2 <= 0;
acc3 <= 0;
end
else
begin
/*perform accumulation process*/
acc1 <= acc1 + ip_data1;
acc2 <= acc2 + acc1;
acc3 <= acc3 + acc2;
end
/*DECIMATION STAGE (MCLKOUT/ WORD_CLK)
*/
always @ (posedge mclk1 or posedge reset)
if (reset)
word_count <= 0;
else
word_count <= word_count + 1;
always @ (word_count)
word_clk <= word_count[7];
/*DIFFERENTIATOR (including decimation stage)
Perform the differentiation stage (FIR) at a
lower speed.
WORD_CLK
ACC3
DIFF1
DIFF3
+
–
+
–
DIFF2
Z–1
–
+
–
Z–1
04718-
022
Figure 26. Differentiator
Z = one sample delay
WORD_CLK = output word rate
*/
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| AD7400YRWZ-REEL7 | 功能描述:IC MODULATOR SIGMA-DELTA 16-SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤 |
| AD7401 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Isolated Sigma-Delta Modulator |
| AD7401_0612 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Isolated Sigma-Delta Modulator |
| AD7401A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Isolated Sigma-Delta Modulator |
| AD7401AYRWZ | 功能描述:IC MODULATOR SIGMA-DELTA 16SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1 系列:microPOWER™ 位數(shù):8 采樣率（每秒）:1M 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:- 電壓電源:模擬和數(shù)字 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:24-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:24-VQFN 裸露焊盤（4x4） 包裝:Digi-Reel® 輸入數(shù)目和類型:8 個(gè)單端，單極 產(chǎn)品目錄頁面:892 (CN2011-ZH PDF) 其它名稱:296-25851-6 |
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