參數(shù)資料
型號: AD7367BRUZ-500RL7
廠商: Analog Devices Inc
文件頁數(shù): 13/28頁
文件大小: 0K
描述: IC ADC 14BIT SAR 1MSPS 24TSSOP
設(shè)計資源: Driving the AD7366/7 Bipolar SAR ADC in Low-Distortion DC-Coupled Appls (CN0042)
標準包裝: 500
位數(shù): 14
采樣率(每秒): 500k
數(shù)據(jù)接口: DSP,MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 2
功率耗散(最大): 88.8mW
電壓電源: 模擬和數(shù)字,雙 ±
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 帶卷 (TR)
輸入數(shù)目和類型: 4 個單端,單極;4 個單端,雙極
AD7366-5/AD7367-5
Rev. A | Page 20 of 28
MODES OF OPERATION
The mode of operation for the AD7366-5/AD7367-5 is selected
by the (logic) state of the CNVST signal at the end of a conver-
sion. There are two possible modes of operation: normal mode
and shutdown mode. These modes of operation are designed to
provide flexible power management options, which can be
chosen to optimize the power dissipation/throughput rate
ratio for differing application requirements.
NORMAL MODE
Normal mode is intended for applications needing fast
throughput rates because the user does not have to worry
about any power-up times (with the AD7366-5/AD7367-5
remaining fully powered at all times). Figure 22 shows the
normal mode of operation for the AD7366-5, while Figure 23
illustrates normal mode for the AD7367-5.
The conversion is initiated on the falling edge of CNVST as
described in the
section. To ensure that
the part remains fully powered up at all times,
CNVST must be
at a logic high state prior to the BUSY signal going low. If
CNVST is at a logic low state when the BUSY signal goes low,
the analog circuitry powers down and the part ceases converting.
The BUSY signal remains high for the duration of the conversion.
The CS pin must be brought low to bring the data bus out of
three-state; subsequently 12 SCLK cycles are required to read
the conversion result from the AD7366-5, while 14 SCLK cycles
are required to read from the AD7367-5. The DOUT lines return
to three-state only when CS is brought high. If CS is left low for
a further 12 SCLK cycles for the AD7366-5 or 14 SCLK cycles
for the AD7367-5, the result from the other on-chip ADC is
also accessed on the same DOUT line, as shown in
and
(see the
section).
After 24 SCLK cycles have elapsed for the AD7366-5 and 28 SCLK
cycles have elapsed for the AD7367-5, the DOUT line returns to
three-state when CS is brought high (not on the 24th or 28th SCLK
falling edge). If CS is brought high prior to this, the DOUT line
returns to three-state at that point. Thus, CS must be brought
high once the read is completed because the bus does not
automatically return to three-state upon completion of the
dual result read.
Once a data transfer is complete and DOUTA and DOUTB have
returned to three-state, another conversion can be initiated after
the quiet time, tQUIET, has elapsed by bringing CNVST low again.
CNVST
BUSY
SCLK
t2
t1
t3
SERIAL READ OPERATION
CS
tCONVERT
tQUIET
1
12
06
84
2-
0
24
BUSY
Figure 22. Normal Mode Operation for the AD7366-5
t2
t1
t3
CS
SCLK
SERIAL READ OPERATION
1
14
tCONVERT
tQUIET
CNVST
06
84
2-
0
25
Figure 23. Normal Mode Operation for the AD7367-5
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