t3 t2 t
參數(shù)資料
型號(hào): AD73360ASUZ-REEL
廠商: Analog Devices Inc
文件頁數(shù): 33/35頁
文件大?。?/td> 0K
描述: IC ANALOG FRONT END 6CH 44-TQFP
標(biāo)準(zhǔn)包裝: 1,500
位數(shù): 16
通道數(shù): 6
功率(瓦特): 80mW
電壓 - 電源,模擬: 2.7 V ~ 3.3 V
電壓 - 電源,數(shù)字: 2.7 V ~ 3.3 V
封裝/外殼: 44-TQFP
供應(yīng)商設(shè)備封裝: 44-TQFP(10x10)
包裝: 帶卷 (TR)
REV. A
AD73360
–7–
t3
t2
t1
Figure 1. MCLK Timing
TO OUTPUT
PIN
+2.1V
100 A
IOL
IOH
CL
15pF
Figure 2. Load Circuit for Timing Specifications
t3
t1
t2
t13
* SCLK IS INDIVIDUALLY PROGRAMMABLE
IN FREQUENCY (MCLK/4 SHOWN HERE).
t4
t5
t6
MCLK
SCLK*
Figure 3. SCLK Timing
t11
t7
t9
t10
t12
t7
t8
SE (I)
SCLK (O)
SDIFS (I)
SDI (I)
SDOFS (O)
SDO (O)
THREE-
STATE
THREE-
STATE
THREE-
STATE
D15
D2
D1
D0
D14
D15
D1
D14
D15
t8
D0
Figure 4. Serial Port (SPORT)
VIN – dBm0
–85
5
–75
–65
–55
–45
–35
–25
–15
–5
80
70
–10
S/(N+D)
dB
30
20
10
0
50
40
60
3.17
Figure 5a. S/(N+D) vs. VIN (ADC @ 3 V) Over Voiceband
Bandwidth (300 Hz–3.4 kHz)
VIN – dBm0
–85
5
–75
–65
–55
–45
–35
–25
–15
–5
80
70
–10
S/(N+D)
dB
30
20
10
0
50
40
60
3.17
Figure 5b. S/(N+D) vs. VIN (ADC @ 5 V) Over Voiceband
Bandwidth (300 Hz–3.4 kHz)
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