- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1980 > AD73311ARSZ (Analog Devices Inc)IC ANALOG FRONT END 20-SSOP PDF資料下載
參數(shù)資料
| 型號： | AD73311ARSZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ANALOG FRONT END 20-SSOP |
| 標(biāo)準(zhǔn)包裝： | 66 |
| 位數(shù)： | 16 |
| 通道數(shù)： | 2 |
| 功率（瓦特）： | 50mW |
| 電壓 - 電源，模擬： | 3V |
| 電壓 - 電源，數(shù)字： | 3V |
| 封裝/外殼： | 20-SSOP（0.209"，5.30mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 20-SSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 799 (CN2011-ZH PDF) |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁當(dāng)前第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
AD73311
–29–
REV. B
APPENDIX B
This section describes a typical sequence in programming a
single codec to operate in mixed mode. The device is connected
in Nonframe Sync Loop-Back Mode (see Figure 14), which
allows the DSP’s Tx Reg to determine how many words are sent
to the device. In Step 1, the part has just been reset and on the
first output event the codec presents an invalid output word
1.
The DSP’s Tx Reg contains a control word that programs CRA
with the data word 0x03, which will put the device in mixed
mode. In Step 2, the control word from the DSP’s Tx Reg has
been sent to the codec’s SPORT and the output word has been
received by the DSP’s Rx Reg. The Tx Register raises the
SDIFS to send a control word that will program CRB of the
codec. In Step 3 the SCLK and sample rate are set by program-
ming CRB. In Step 4, the analog sections of the device are
powered up by programming CRC, while in Step 5, the encoder
gain is set to 0 dB via CRD. In Step 6, the DAC register is
updated by the contents of the serial register. Alternately, a
register read cycle could be introduced instead of the DAC load
in Step 6
2. Steps 7 and 8 show another ADC read, DAC write
cycle.
NOTES
1Data output by the codec in program mode is invalid and should not be inter-
preted as ADC data. The only exception to this is output caused by register
reads or CEE being enabled on control word writes.
2In mixed mode, it may be necessary to terminate a control word write to a
device with a control word read to that device in order to ensure that the next
ADC sample is correct. Alternatively the ADC word can either be discarded or,
if this is not possible, it can be rebuilt by incrementing the “address field”
within the 16-bit word.
DSP TX REG
CONTROL WORD 1
1 0 000 000 00000011
ADC WORD 1 *
0000 0000 0000 0000
DON'T CARE
XXXX XXXX XXXX XXXX
STEP 1
DSP TX REG
DEVICE 1
CONTROL WORD 1
1 0 000 001 00001111
CONTROL WORD 1
1 0 000 000 00000011
ADC WORD 1 *
0000 0000 0000 0000
DSP RX REG
STEP 2
DSP TX REG
DEVICE 1
CONTROL WORD 1
1 0 000 010 00000001
CONTROL WORD 1
1 0 000 001 00001111
DON'T CARE
XXXX XXXX XXXX XXXX
DSP RX REG
STEP 3
DSP TX REG
DEVICE 1
CONTROL WORD 1
1 0 000 000 00000001
CONTROL WORD 1
1 0 000 010 00000001
DON'T CARE
XXXX XXXX XXXX XXXX
DSP RX REG
STEP 4
DSP TX REG
DEVICE 1
DAC WORD 1
0100 0000 0000 0000
CONTROL WORD 1
1 0 000 011 00100000
DON'T CARE
XXXX XXXX XXXX XXXX
DSP RX REG
STEP 5
DSP TX REG
DEVICE 1
DAC WORD 1
0011 1111 1111 1111
DAC WORD 1
0100 0000 0000 0000
DON'T CARE
XXXX XXXX XXXX XXXX
DSP RX REG
STEP 6
DSP TX REG
DAC WORD 1
0011 1111 1111 1111
ADC WORD 1
0100 0000 0000 0000
DON'T CARE
XXXX XXXX XXXX XXXX
DSP RX REG
STEP 7
DSP TX REG
DEVICE 1
DAC WORD 1
0100 0000 0000 0000
DAC WORD 1
0011 1111 1111 1111
ADC WORD 1
1000 0000 0000 0000
DSP RX REG
STEP 8
*ADC SAMPLES DURING PROGRAM MODE ARE INVALID.
DEVICE 1
DSP RX REG
DEVICE 1
Figure 34. Programming a Single AD73311 for Mixed Mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD73322LARUZ-REEL | IC PROCESSOR FRONTEND DL 28TSSOP |
| AD73322LYRZ | IC ANALOG FRONT END DUAL 28-SOIC |
| AD73360ARZ | IC PROCESSOR FRONTEND 6CH 28SOIC |
| AD7352YRUZ-500RL7 | IC ADC DUAL 12BIT 3MSPS 16TSSOP |
| AD7356YRUZ-500RL7 | IC ADC DUAL 12BIT 5MSPS 16TSSOP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD73311ARSZ-REEL | 功能描述:IC ANALOG FRONT END 20-SSOP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD73311ARZ | 功能描述:IC PROCESSOR FRONT END LP 20SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD73311ARZ-REEL | 功能描述:IC PROCESSOR FRONT END LP 20SOIC RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模擬前端 (AFE) 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:2,500 系列:- 位數(shù):- 通道數(shù):2 功率（瓦特）:- 電壓 - 電源，模擬:3 V ~ 3.6 V 電壓 - 電源，數(shù)字:3 V ~ 3.6 V 封裝/外殼:32-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:32-QFN（5x5） 包裝:帶卷 (TR) |
| AD73311L | 制造商:AD 制造商全稱:Analog Devices 功能描述:Low Cost, Low Power CMOS General Purpose Analog Front End |
| AD73311LAR | 制造商:Analog Devices 功能描述:Audio Codec 1ADC / 1DAC 16-Bit 20-Pin SOIC W 制造商:Rochester Electronics LLC 功能描述:SINGLE-CHANNEL AFE I.C. - Bulk |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。