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參數(shù)資料
| 型號： | AD7329BRUZ-REEL7 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 2/41頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 12BIT+SAR 8CHAN 24-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 30mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 8 個單端，單極；8 個單端，雙極；4 個差分，單極；4 個差分，雙極 |
| 配用： | EVAL-AD7329CBZ-ND - BOARD EVALUATION FOR AD7329CBZ |
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Data Sheet
AD7329
Rev. B | Page 9 of 40
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
1
2
3
4
5
6
7
8
10
20
21
22
23
24
19
18
17
16
15
14
13
12
11
DIN
DGND
AGND
ADCIN+
VSS
REFIN/REFOUT
CS
DGND
DOUT
VDRIVE
ADCIN–
VDD
VCC
MUXOUT+
VIN0
VIN5
VIN4
VIN1
MUXOUT–
VIN2
VIN7
VIN6
VIN3
SCLK
AD7329
TOP VIEW
(Not to Scale)
05402-
003
Figure 3. TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Descriptions
24
SCLK
Serial Clock, Logic Input. A serial clock input provides the SCLK used for accessing the data from the AD7329.
This clock is also used as the clock source for the conversion process.
22
DOUT
Serial Data Output. The conversion output data is supplied to this pin as a serial data stream. The bits are
clocked out on the falling edge of the SCLK input, and 16 SCLKs are required to access the data. The data
stream consists of three channel identification bits, the sign bit, and 12 bits of conversion data. The data is
provided MSB first (see the Serial Interface section).
1
CS
Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the
AD7329 and frames the serial data transfer.
2
DIN
Data In. Data to be written to the on-chip registers is provided on this input and is clocked into the register
on the falling edge of SCLK (see the Registers section).
21
VDRIVE
Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the interface operates.
This pin should be decoupled to DGND. The voltage at this pin can be different than that at VCC but should
not exceed VCC by more than 0.3 V.
3, 23
DGND
Digital Ground. Ground reference point for all digital circuitry on the AD7329. The DGND and AGND voltages
should ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
4
AGND
Analog Ground. Ground reference point for all analog circuitry on the AD7329. All analog input signals and
any external reference signal should be referred to this AGND voltage. The AGND and DGND voltages should
ideally be at the same potential and must not be more than 0.3 V apart, even on a transient basis.
5
REFIN/REFOUT
Reference Input/Reference Output. The on-chip reference is available on this pin for use external to the AD7329.
The nominal internal reference voltage is 2.5 V, which appears at the pin. A 680 nF capacitor should be placed
on the reference pin. Alternatively, the internal reference can be disabled and an external reference can be
applied to this input. On power-up, the external reference mode is the default condition (see the Reference
section).
20
VCC
Analog Supply Voltage, 2.7 V to 5.25 V. This is the supply voltage for the ADC core on the AD7329. This supply
should be decoupled to AGND.
19
VDD
Positive Power Supply Voltage. This is the positive supply voltage for the analog input section.
6
VSS
Negative Power Supply Voltage. This is the negative supply voltage for the analog input section.
7
ADCIN+
Positive ADC Input. This pin allows access to the on-chip track-and-hold. The voltage applied to this pin is still
a high voltage signal (±10 V, ±5 V, ±2.5 V, or 0 V to +10 V).
8
MUXOUT+
Positive Multiplexer Output. The output of the multiplexer appears at this pin. The voltage at this pin is still a
high voltage signal equivalent to the voltage applied to the VIN+ input channel, as selected in the control
register or sequence register. If no external filtering or buffering is required, this pin should be tied to the
ADCIN+ pin.
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