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參數(shù)資料
| 型號(hào)： | AD7324BRUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 24/37頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT+SAR 4CHAN 16-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 30mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個(gè)單端，單極；4 個(gè)單端，雙極；2 個(gè)差分，單極；2 個(gè)差分，雙極 |
| 配用： | EVAL-AD7324CBZ-ND - BOARD EVALUATION FOR AD7324CBZ |
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Data Sheet
AD7324
Rev. B | Page 29 of 36
AUTOSHUTDOWN MODE
(PM1 = 1, PM0 = 0)
Once the autoshutdown mode is selected, the AD7324 auto-
matically enters shutdown on the 15th SCLK rising edge. In
autoshutdown mode, all internal circuitry is powered down. The
AD7324 retains information in the registers during autoshutdown.
The track-and-hold is in hold mode during autoshutdown. On
the rising CS edge, the track-and-hold, which was in hold during
shutdown, returns to track as the AD7324 begins to power up.
The power-up from autoshutdown is 500 s.
When the control register is programmed to transition to
autoshutdown mode, it does so on the 15th SCLK rising edge.
Figure 48 shows the part entering autoshutdown mode. Once in
autoshutdown mode, the CS signal must remain low to keep the
part in autoshutdown mode. The AD7324 automatically begins to
power up on the CS rising edge. The tPOWER-UP for autoshutdown
is required before a valid conversion, initiated by bringing the
CS signal low, can take place. Once this valid conversion is
rising edge. The CS signal must remain low again to keep the
part in autoshutdown mode.
AUTOSTANDBY MODE
(PM1 = 0, PM0 =1)
In autostandby mode, portions of the AD7324 are powered
down, but the on-chip reference remains powered up. The
reference bit in the control register should be 1 to ensure that
the on-chip reference is enabled. This mode is similar to
autoshutdown, but allows the AD7324 to power up much faster.
This allows faster throughput rates to be achieved.
As is the case with the autoshutdown mode, the AD7324 enters
standby on the 15th SCLK rising edge once the control register is
updated (see Figure 48). The part retains information in the
registers during standby. Once in autostandby mode, the CS
signal must remain low to keep the part in autostandby mode.
The AD7324 remains in standby until it receives a CS rising
edge. The ADC begins to power up on the CS rising edge. On
the CS rising edge, the track-and-hold, which was in hold mode
while the part was in standby, returns to track. The power-up
time from standby is 700 ns.
The user should ensure that 700 ns have elapsed before bringing
CS low to attempt a valid conversion. Once this valid conversion
rising edge. The CS signal must remain low to keep the part in
standby mode.
Figure 48 shows the part entering autoshutdown mode. The
sequence of events is the same when entering autostandby mode.
In Figure 48, the power management bits are configured for
autoshutdown. For autostandby mode, the power management
bits, PM1 and PM0, should be set to 0 and 1, respectively.
CS
1
16
15
1
16
15
SCLK
SDATA
DIN
VALID DATA
DATA INTO CONTROL REGISTER
tPOWER-UP
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,
PM1 = 1, PM0 = 0
PART ENTERS SHUTDOWN MODE
ON THE 15TH RISING SCLK EDGE
AS PM1 = 1, PM0 = 0
PART BEGINS TO POWER
UP ON CS RISING EDGE
THE PART IS FULLY POWERED UP
ONCE
tPOWER-UP HAS ELAPSED
04864-
042
Figure 48. Entering Autoshutdown/Autostandby Mode
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