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參數(shù)資料
| 型號： | AD7324BRUZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 17/37頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 12BIT+SAR 4CHAN 16-TSSOP |
| 標準包裝： | 2,500 |
| 位數(shù)： | 12 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 30mW |
| 電壓電源： | 雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，單極；4 個單端，雙極；2 個差分，單極；2 個差分，雙極 |
| 配用： | EVAL-AD7324CBZ-ND - BOARD EVALUATION FOR AD7324CBZ |
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Data Sheet
AD7324
Rev. B | Page 23 of 36
The four analog input channels can be configured as three pseudo differential analog inputs, two pseudo differential inputs, two true
differential input pairs, or four single-ended analog inputs.
Table 10. Analog Input Configuration Selection
Mode 1 = 1, Mode 0 = 1
Mode 1 = 1, Mode 0 = 0
Mode 1 = 0, Mode 0 =1
Mode 1 = 0, Mode 0 = 0
Channel Address Bits
3 Pseudo Differential Inputs
2 Fully Differential Inputs
2 Pseudo Differential Inputs
4 Single-Ended Inputs
ADD1
ADD0
VIN+
VIN
VIN+
VIN
VIN+
VIN
VIN+
VIN
0
VIN0
VIN3
VIN0
VIN1
VIN0
VIN1
VIN0
AGND
0
1
VIN1
VIN3
VIN0
VIN1
VIN0
VIN1
AGND
1
0
VIN2
VIN3
VIN2
VIN3
VIN2
VIN3
VIN2
AGND
1
Not a valid selection
VIN2
VIN3
VIN2
VIN3
AGND
Table 11. Power Mode Selection
PM1
PM0
Description
1
Full Shutdown Mode. In this mode, all internal circuitry on the AD7324 is powered down. Information in the control register
is retained when the AD7324 is in full shutdown mode.
1
0
Autoshutdown Mode. The AD7324 enters autoshutdown on the 15th SCLK rising edge when the control register is updated.
All internal circuitry is powered down in autoshutdown.
0
1
Autostandby Mode. In this mode, all internal circuitry is powered down excluding the internal reference. The AD7324 enters
autostandby mode on the 15th SCLK rising edge after the control register is updated.
0
Normal Mode. All internal circuitry is powered up at all times.
Table 12. Sequencer Selection
Seq1
Seq2
Sequence Type
0
The channel sequencer is not used. The analog channel, selected by programming the ADD1 bit and ADD0 bit in the
control register, selects the next channel for conversion.
0
1
Uses sequence of channels that were previously programmed in the sequence register for conversion. The AD7324 starts
converting on the lowest channel in the sequence. The channels are converted in ascending order. If uninterrupted, the
AD7324 keeps converting the sequence. The range for each channel defaults to the range previously written into the
range register.
1
0
Used in conjunction with the channel address bits in the control register. This allows continuous conversions on a
consecutive sequence of channels, from Channel 0 up to and including a final channel selected by the channel address bits
in the control register. The range for each channel defaults to the range previously written into the range register.
1
The channel sequencer is not used. The analog channel, selected by programming the ADD1 bit and ADD0 bit in the
control register, selects the next channel for conversion.
SEQUENCE REGISTER
The sequence register on the AD7324 is a 4-bit, write-only register. Each of the four analog input channels has one corresponding bit in
the sequence register. To select a channel for inclusion in the sequence, set the corresponding channel bit to 1 in the sequence register.
MSB
LSB
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
Write
Register Select 1
Register Select 2
VIN0
VIN1
VIN2
VIN3
0
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