參數(shù)資料
型號(hào)： AD7322BRUZ-REEL7
廠商： Analog Devices Inc
文件頁數(shù)： 21/37頁
文件大?。?/td> 0K
描述： IC ADC 12BIT+ SAR 2CHAN 14TSSOP
標(biāo)準(zhǔn)包裝： 1,000
位數(shù)： 12
采樣率（每秒）： 1M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 30mW
電壓電源： 雙 ±
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 14-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 14-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)單端，單極；2 個(gè)單端，雙極；1 個(gè)差分，單極；1 個(gè)差分，雙極
配用： EVAL-AD7322CBZ-ND - BOARD EVALUATION FOR AD7322
Data Sheet
AD7322
Rev. B | Page 27 of 36
MODES OF OPERATION
The AD7322 has several modes of operation that are designed
to provide flexible power management options. These options
can be chosen to optimize the power dissipation/throughput
rate ratio for different application requirements. The mode of
operation of the AD7322 is controlled by the power manage-
ment bits, Bit PM1 and Bit PM0, in the control register as shown
in Table 11. The default mode is normal mode, in which all
internal circuitry is fully powered up.
NORMAL MODE (PM1 = PM0 = 0)
This mode is intended for the fastest throughput rate perfor-
mance, with the AD7322 being fully powered up at all times.
Figure 45 shows the general operation of the AD7322 in
normal mode.
The conversion is initiated on the falling edge of CS, and the
track-and-hold enters hold mode as described in the Serial
Interface section. Data on the DIN line during the 16 SCLK
transfer is loaded into one of the on-chip registers if the write
bit is set. The register is selected by programming the register
select bits (see Figure 45).
1
16
2 LEADING ZEROS, CHANNEL I.D. BIT, SIGN BIT
+ CONVERSION RESULT
DATA INTO CONTROL/RANGE REGISTER
SCLK
CS
DOUT
DIN
04863-
035
Figure 45. Normal Mode
The AD7322 remains fully powered up at the end of the
conversion if both PM1 and PM0 contain 0 in the control
register.
To complete the conversion and access the conversion result,
16 serial clock cycles are required. At the end of the conversion,
CS can idle either high or low until the next conversion.
When the data transfer is complete, another conversion can be
initiated after the quiet time, tQUIET, has elapsed.
FULL SHUTDOWN MODE (PM1 = PM0 = 1)
In this mode, all internal circuitry on the AD7322 is powered
down. The part retains information in the registers during full
shutdown. The AD7322 remains in full shutdown mode until
the power management bits, Bit PM1 and Bit PM0, in the
control register are changed.
A write to the control register with PM1 = 1 and PM0 = 1 places
the part into full shutdown mode. The AD7322 enters full shut-
down mode on the 15th SCLK rising edge when the control register
is updated.
If a write to the control register occurs while the part is in full
shutdown mode with the power management bits, Bit PM1 and
Bit PM0, set to 0 (normal mode), the part begins to power up
on the 15th SCLK rising edge when the control register is updated.
Figure 46 shows how the AD7322 is configured to exit full
shutdown mode. To ensure the AD7322 is fully powered up,
tPOWER-UP for full shutdown mode should elapse before the next
CS falling edge.
CS
1
16
1
16
SCLK
SDATA
DIN
INVALID DATA
CHANNEL IDENTIFIER BITS + CONVERSION RESULT
DATA INTO CONTROL REGISTER
tPOWER-UP
THE PART IS FULLY POWERED UP
ONCE
tPOWER-UP HAS ELAPSED
CONTROL REGISTER IS LOADED ON THE FIRST 15 CLOCKS,
PM1 = 0, PM0 = 0
TO KEEP THE PART IN NORMAL MODE, LOAD PM1 = PM0 = 0
IN CONTROL REGISTER
PART IS IN FULL
SHUTDOWN
PART BEGINS TO POWER UP ON THE 15TH
SCLK RISING EDGE AS PM1 = PM0 = 0
04863-
041
Figure 46. Exiting Full Shutdown Mode
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