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參數(shù)資料
| 型號： | AD7306JRZ-REEL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 4/8頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TXRX RS232/RS422 5V 24-SOIC |
| 標(biāo)準(zhǔn)包裝： | 1,000 |
| 類型： | 收發(fā)器 |
| 驅(qū)動器/接收器數(shù)： | 3/3 |
| 規(guī)程： | RS232 |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 24-SOIC（0.295"，7.50mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-SOIC W |
| 包裝： | 帶卷 (TR) |
AD7306
–4–
REV. B
PIN FUNCTION DESCRIPTION
SOIC
DIP
Pin
Mnemonic
Function
1
19
V+
Internally Generated Positive Supply (+9 V nominal). A 0.1
F capacitor must be connected
between this pin and GND.
2, 3
20, 22
C1+, C1–
External Capacitor 1 Terminals. A 0.1
F capacitor must be connected between these pins.
423
R2IN
RS-232 Receiver R2 Input. This input accepts RS-232 input voltages.
524
T1OUT
RS-232 Transmitter (Driver) T1 Output (Typically
±7.5 V).
61
T2OUT
RS-232 Transmitter (Driver) T2 Output (Typically
±7.5 V).
72
VCC
Power Supply Input (5 V
± 5%).
83
R1IN (B)
RS-422 Receiver R1, Differential Input B.
94
R1IN/R1IN (A)
Receiver R1 Input. May be configured to accept either single ended RS-232 levels or
differential RS-422 levels. It is configured using the 232/422 SEL pin.
10
5
T3OUT (B)
RS-422 Transmitter (Driver) T3, Differential Output B.
11
6
T3OUT (A)
RS-232 Transmitter (Driver) T3, Differential Output A.
12, 13
16, 21
NC
No Connect Pins.
14, 18
7, 11
GND
Ground Pin. Must be connected to 0 V.
15
8
232/422 SEL
Select Input. This input configures Receiver R1 to accept either RS-232 or RS-422 signal lev-
els. A Logic 1 on this input selects 232 operation while a Logic 0 selects 422 operation.
16
9
T3IN
TTL/CMOS Input to the RS-422 Transmitter T3.
17
10
R1OUT
TTL/CMOS Output from Receiver R1.
19
12
T2IN
TTL/CMOS Input to RS-232 Transmitter T2.
20
13
T1IN
TTL/CMOS Input to RS-232 Transmitter T1.
21
14
R2OUT
TTL/CMOS Output from Receiver R2.
22, 23
15, 17
C2+, C2–
External Capacitor 2 Terminals. A 0.1
F capacitor must be connected between these pins.
24
18
V–
Internally Generated Negative Supply (–9 V nominal). A 0.1
F capacitor must be connected
between this pin and GND.
PIN CONFIGURATIONS
SOIC
V+
C1+
C1–
V–
C2–
C2+
GND
NC
NC = NO CONNECT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
16
15
14
13
20
19
18
17
AD7306
SOIC
TOP VIEW
(Not to Scale)
GND
R1
IN /R1IN (A)
T2
OUT
T1
OUT
R2
IN
R1
IN (B)
T3
OUT (B)
R2
OUT
T3
IN
232/422 SEL
V
CC
R1
OUT
T1
IN
T2
IN
T3
OUT (A)
DIP
R1
IN /R1IN (A)
V+
C1+
C1–
V–
C2–
C2+
GND
NC
T2
OUT
T1
OUT
R2
IN
R1
IN (B)
T3
OUT (B)
R2
OUT
T3
IN
232/422 SEL
V
CC
NC = NO CONNECT
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
16
15
14
13
20
19
18
17
AD7306
DIP
TOP VIEW
(Not to Scale)
GND
R1
OUT
T1
IN
T2
IN
T3
OUT (A)
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