- 鎮ㄧ従(xi脿n)鍦ㄧ殑浣嶇疆锛�璨疯常IC缍�(w菐ng) > PDF鐩寗1980 > AD7303BRM (Analog Devices Inc)IC DAC 8BIT DUAL R-R 8-MSOP PDF璩囨枡涓嬭級
鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉(h脿o)锛� | AD7303BRM |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 5/16闋� |
| 鏂囦欢澶у皬锛� | 0K |
| 鎻忚堪锛� | IC DAC 8BIT DUAL R-R 8-MSOP |
| 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� | Data Converter Fundamentals DAC Architectures |
| 妯�(bi膩o)婧�(zh菙n)鍖呰锛� | 50 |
| 瑷�(sh猫)缃檪(sh铆)闁擄細 | 1.2µs |
| 浣嶆暩(sh霉)锛� | 8 |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | 涓茶 |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 2 |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 6.93mW |
| 宸ヤ綔婧害锛� | -40°C ~ 105°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-MSOP |
| 鍖呰锛� | 绠′欢 |
| 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� | 2 闆诲锛屽柈妤�锛�2 闆诲锛岄洐妤� |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 833k |
AD7303
鈥�13鈥�
REV. 0
SCLK
VDD
10k
AD7303
DIN
SYNC
SCLK
VDD
REF
POWER
+5V
REGULATOR
VOUTB
VOUTA
AGND
10F
0.1F
VDD
10k
DATA
VDD
10k
SYNC
Figure 32. AD7303 in Opto-Isolated Interface
Decoding Multiple AD7303
The SYNC pin on the AD7303 can be used in applications to
decode a number of DACs. In this application, all DACs in the
system receive the same serial clock and serial data, but only the
SYNC
to one of the DACs will be active at any one time allow-
ing access to two channels in this eight-channel system. The
74HC139 is used as a 2- to 4-line decoder to address any of the
DACs in the system. To prevent timing errors from occurring,
the enable input should be brought to its inactive state while the
coded address inputs are changing state. Figure 33 shows a dia-
gram of a typical setup for decoding multiple AD7303 devices in
a system.
ENABLE
74HC139
AD7303
SYNC
DIN
SCLK
DIN
SCLK
DGND
CODED
ADDRESS
1A
1B
1Y0
1Y1
1Y2
1Y3
VCC
VDD
1
G
AD7303
SYNC
DIN
SCLK
AD7303
SYNC
DIN
SCLK
AD7303
SYNC
DIN
SCLK
Figure 33. Decoding Multiple AD7303 Devices in a System
AD7303 as a Digitally Programmable Window Detector
A digitally programmable upper/lower limit detector using the
two DACs in the AD7303 is shown in Figure 34. The upper
and lower limits for the test are loaded to DACs A and B which,
in turn, set the limits on the CMP04. If a signal at the VIN input
is not within the programmed window, a led will indicate the fail
condition.
AD7303
VDD
+5V
VOUTA
GND
0.1F
REF
VIN
PASS/
FAIL
1/2
CMP04
1/6 74HC05
FAIL
PASS
1k
0.1F
10F
SCLK
DIN
SYNC
SCLK
DIN
SYNC
1k
VOUTB
Figure 34. Window Detector Using AD7303
Programmable Current Source
Figure 35 shows the AD7303 used as the control element of a
programmable current source. In this circuit, the full-scale cur-
rent is set to 1 mA. The output voltage from the DAC is applied
across the current setting resistor of 4.7 k
in series with the
full-scale setting resistor of 470
. Suitable transistors to place
in the feedback loop of the amplifier include the BC107 and the
2N3904, which enable the current source to operate from a min
VSOURCE of 6 V. The operating range is determined by the oper-
ating characteristics of the transistor. Suitable amplifiers in-
clude the AD820 and the OP295, both having rail-to-rail
operation on their outputs. The current for any digital input
code can be calculated as follows:
I = 2
脳 V
REF
脳 D/(5E + 3 脳 256) mA
4.7k
470
+5V
LOAD
VSOURCE
AD7303
VOUTA
10F
0.1F
VDD = +5V
VDD
GND
AD780/ REF192
WITH VDD = +5V
REF
SCLK
DIN
SYNC
GND
VOUT
VIN
0.1F
SERIAL
INTERFACE
EXT
REF
AD820/
OP295
Figure 35. Programmable Current Source
鐩搁棞(gu膩n)PDF璩囨枡 |
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鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| AD7303BRM-REEL | 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:DAC 2-CH Current Steering 8-bit 8-Pin MSOP T/R 鍒堕€犲晢:Analog Devices 鍔熻兘鎻忚堪:DAC 2CH CURRENT STEERING 8BIT 8MSOP - Tape and Reel 鍒堕€犲晢:Rochester Electronics LLC 鍔熻兘鎻忚堪:DUAL SERIAL 8-BIT SINGLE SUPPLY DAC I.C. - Tape and Reel |
| AD7303BRM-REEL7 | 鍔熻兘鎻忚堪:IC DAC 8BIT DUAL R-R 8-MSOP T/R RoHS:鍚� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:2,400 绯诲垪:- 瑷�(sh猫)缃檪(sh铆)闁�:- 浣嶆暩(sh霉):18 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:3 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 鍔熺巼鑰楁暎锛堟渶澶э級:- 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:36-TFBGA 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:36-TFBGA 鍖呰:甯跺嵎 (TR) 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:* 閲囨ǎ鐜囷紙姣忕锛�:* |
| AD7303BRMZ | 鍔熻兘鎻忚堪:IC DAC 8BIT DUAL R-R 8-MSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 妯�(bi膩o)婧�(zh菙n)鍖呰:50 绯诲垪:- 瑷�(sh猫)缃檪(sh铆)闁�:4µs 浣嶆暩(sh霉):12 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:2 闆诲闆绘簮:鍠浕婧� 鍔熺巼鑰楁暎锛堟渶澶э級:- 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:8-uMAX 鍖呰:绠′欢 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:2 闆诲锛屽柈妤� 閲囨ǎ鐜囷紙姣忕锛�:* 鐢�(ch菐n)鍝佺洰閷勯爜闈�:1398 (CN2011-ZH PDF) |
| AD7303BRMZ-REEL | 鍔熻兘鎻忚堪:IC DAC 8BIT DUAL R-R 8-MSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 鐗硅壊鐢�(ch菐n)鍝�:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/掳C Reference 妯�(bi膩o)婧�(zh菙n)鍖呰:91 绯诲垪:- 瑷�(sh猫)缃檪(sh铆)闁�:4µs 浣嶆暩(sh霉):10 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛屼覆琛�锛孲PI? 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:8 闆诲闆绘簮:鍠浕婧� 鍔熺巼鑰楁暎锛堟渶澶э級:2.7mW 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:14-WFDFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:14-DFN-EP锛�4x3锛� 鍖呰:绠′欢 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:8 闆诲锛屽柈妤� 閲囨ǎ鐜囷紙姣忕锛�:* |
| AD7303BRMZ-REEL7 | 鍔熻兘鎻忚堪:IC DAC 8BIT DUAL R-R 8-MSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 鏁�(sh霉)妯¤綁(zhu菐n)鎻涘櫒 绯诲垪:- 鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″:LTC263x 12-, 10-, and 8-Bit VOUT DAC Family 鐗硅壊鐢�(ch菐n)鍝�:LTC2636 - Octal 12-/10-/8-Bit SPI VOUT DACs with 10ppm/掳C Reference 妯�(bi膩o)婧�(zh菙n)鍖呰:91 绯诲垪:- 瑷�(sh猫)缃檪(sh铆)闁�:4µs 浣嶆暩(sh霉):10 鏁�(sh霉)鎿�(j霉)鎺ュ彛:MICROWIRE?锛屼覆琛�锛孲PI? 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:8 闆诲闆绘簮:鍠浕婧� 鍔熺巼鑰楁暎锛堟渶澶э級:2.7mW 宸ヤ綔婧害:-40°C ~ 85°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:14-WFDFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:14-DFN-EP锛�4x3锛� 鍖呰:绠′欢 杓稿嚭鏁�(sh霉)鐩拰椤炲瀷:8 闆诲锛屽柈妤� 閲囨ǎ鐜囷紙姣忕锛�:* |
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