TIMING CHARACTERISTICS1, 2 Parameter Limit at T
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AD7303BRM
寤犲晢锛� Analog Devices Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 10/16闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC DAC 8BIT DUAL R-R 8-MSOP
鐢�(ch菐n)鍝佸煿瑷�(x霉n)妯″锛� Data Converter Fundamentals
DAC Architectures
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 50
瑷�(sh猫)缃檪(sh铆)闁擄細 1.2µs
浣嶆暩(sh霉)锛� 8
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� 涓茶
杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 2
闆诲闆绘簮锛� 鍠浕婧�
鍔熺巼鑰楁暎锛堟渶澶э級锛� 6.93mW
宸ヤ綔婧害锛� -40°C ~ 105°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-MSOP
鍖呰锛� 绠′欢
杓稿嚭鏁�(sh霉)鐩拰椤炲瀷锛� 2 闆诲锛屽柈妤�锛�2 闆诲锛岄洐妤�
閲囨ǎ鐜囷紙姣忕锛夛細 833k
AD7303
鈥�3鈥�
REV. 0
TIMING CHARACTERISTICS1, 2
Parameter
Limit at TMIN, TMAX (B Version)
Units
Conditions/Comments
t1
33
ns min
SCLK Cycle Time
t2
13
ns min
SCLK High Time
t3
13
ns min
SCLK Low Time
t4
5
ns min
SYNC
Setup Time
t5
5
ns min
Data Setup Time
t6
4.5
ns min
Data Hold Time
t7
4.5
ns min
SYNC
Hold Time
t8
33
ns min
Minimum SYNC High Time
NOTES
1Sample tested at +25
掳C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of V
DD) and timed from a voltage level of (VIL + VIH)/2,
tr and tf should not exceed 1
s on any input.
2See Figures 1 and 2.
SCLK (I)
SYNC (I)
DIN (I)
DB15
DB0
t5
t6
t2
t3
t4
t7
t4
t8
t1
Figure 1. Timing Diagram for Continuous 16-Bit Write
SCLK (I)
SYNC (I)
DIN (I)
DB15
DB8
t5
t6
t2
t3
t4
t7
DB7
DB0
t5
t6
t8
t1
Figure 2. Timing Diagram for 2
脳 8-Bit Writes
(VDD = +2.7 V to +5.5 V; GND = 0 V; Reference = Internal VDD/2 Reference; all specifications
TMIN to TMAX unless otherwise noted)
鐩搁棞(gu膩n)PDF璩囨枡
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