參數(shù)資料
型號(hào)： AD7303BNZ
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： +2.7 V to +5.5 V, Serial Input, Dual Voltage Output 8-Bit DAC
中文描述： SERIAL INPUT LOADING, 1.2 us SETTLING TIME, 8-BIT DAC, PDIP8
封裝： PLASTIC, DIP-8
文件頁數(shù)： 9/16頁
文件大?。?/td> 361K
代理商： AD7303BNZ
REV. 0
–2–
AD7303–SPECIFICATIONS
(VDD = +2.7 V to +5.5 V, Internal Reference; RL = 10 k
to VDD and GND; CL = 100 pF
to GND; all specifications TMIN to TMAX unless otherwise noted)
Parameter
B Versions
1
Units
Conditions/Comments
STATIC PERFORMANCE
Resolution
8
Bits
Relative Accuracy
±1
LSB max
Note 2
Differential Nonlinearity
±1
LSB max
Guaranteed Monotonic
Zero-Code Error @ +25
°C
3
LSB max
All Zeros Loaded to DAC Register
Full-Scale Error
–0.5
LSB typ
All Ones Loaded to DAC Register
Gain Error
3
+1
% FSR typ
Zero-Code Temperature Coefficient
100
V/°C typ
DAC REFERENCE INPUT
REFIN Input Range
1 to VDD/2
V min to max
REFIN Input Impedance
10
Μ typ
Internal Voltage Reference Error
4
±1
% max
OUTPUT CHARACTERISTICS
Output Voltage Range
0 to VDD
V min to max
Output Voltage Settling Time
2
s max
Typically 1.2
s
Slew Rate
7.5
V/
s typ
Digital to Analog Glitch Impulse
0.5
nV-s typ
1 LSB Change Around Major Carry
Digital Feedthrough
0.2
nV-s typ
Digital Crosstalk
0.2
nV-s typ
Analog Crosstalk
±0.2
LSB typ
DC Output Impedance
40
typ
Short Circuit Current
14
mA typ
Power Supply Rejection Ratio
0.0001
%/% max
V
DD = ± 10%
LOGIC INPUTS
Input Current
±10
A max
VINL, Input Low Voltage
0.8
V max
VDD = +5 V
0.6
V max
VDD = +3 V
VINH, Input High Voltage
2.4
V min
VDD = +5 V
2.1
V min
VDD = +3 V
Pin Capacitance
5
pF max
POWER REQUIREMENTS
VDD
2.7/5.5
V min/max
IDD (Normal Mode)
Both DACs Active and Excluding Load Currents,
VDD = 3.3 V
VIH = VDD, VIL = GND
@ +25
°C
2.1
mA max
See Figure 8
TMIN – TMAX
2.3
mA max
VDD = 5.5 V
@ +25
°C
2.7
mA max
TMIN – TMAX
3.5
mA max
IDD (Full Power-Down)
@ +25
°C
80
nA typ
VIH = VDD, VIL = GND
TMIN – TMAX
1
A max
See Figure 19
NOTES
1Temperature ranges are as follows: B Version, –40
°C to +105°C.
2Relative Accuracy is calculated using a reduced digital code range of 15 to 245.
3Gain Error is specified between Codes 15 and 245. The actual error at Code 15 is typically 3 LSB.
4Internal Voltage Reference Error = (Actual V
REF – Ideal VREF/Ideal VREF) 100. Ideal VREF = VDD/2, actual VREF = voltage on reference pin when internal reference
is selected.
Specifications subject to change without notice.
ORDERING GUIDE
Temperature
Package
Model
Range
Options*
AD7303BN
–40
°C to +105°C
N-8
AD7303BR
–40
°C to +105°C
SO-8
AD7303BRM
–40
°C to +105°C
RM-8
*N = Plastic DIP; R = SOIC; RM = microSOIC.
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