參數(shù)資料
型號： AD7303BNZ
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： +2.7 V to +5.5 V, Serial Input, Dual Voltage Output 8-Bit DAC
中文描述： SERIAL INPUT LOADING, 1.2 us SETTLING TIME, 8-BIT DAC, PDIP8
封裝： PLASTIC, DIP-8
文件頁數(shù)： 2/16頁
文件大?。?/td> 361K
代理商： AD7303BNZ
AD7303
–10–
REV. 0
Bit Location
Mnemonic
Description
DB15
INT
/EXT
Selects between internal and external reference.
DB14
X
Uncommitted bit.
DB13
LDAC
Load DAC bit for synchronous update of DAC outputs.
DB12
PDB
Power-down DAC B.
DB11
PDA
Power-down DAC A.
DB10
A
/B
Address bit to select either DAC A or DAC B.
DB9
CR1
Control Bit 1 used in conjunction with CR0 to implement the various data loading functions.
DB8
CR0
Control Bit 0 used in conjunction with CR1 to implement the various data loading functions.
DB7–DB0
Data
These bits contain the data used to update the output of the DACs. DB7 is the MSB and
DB0 the LSB of the 8-bit data word.
CONTROL BITS
LDAC
A
/B
CR1
CR0
Function Implemented
0
X
0
Both DAC registers loaded from shift register.
0
1
Update DAC A input register from shift register.
0
1
0
1
Update DAC B input register from shift register.
0
1
0
Update DAC A DAC register from input register.
0
1
0
Update DAC B DAC register from input register.
0
1
Update DAC A DAC register from shift register.
0
1
Update DAC B DAC register from shift register.
1
0
X
Load DAC A input register from shift register and update
both DAC A and DAC B DAC registers.
1
X
Load DAC B input register from shift register and update
both DAC A and DAC B DAC registers outputs.
INT
/EXT
Function
0
Internal VDD/2 reference selected.
1
External reference selected; this external reference is applied at the REF pin and ranges from
1 V to VDD/2.
PDA
PDB
Function
0
Both DACs active.
0
1
DAC A active and DAC B in power-down mode.
1
0
DAC A in power-down mode and DAC B active.
1
Both DACs powered down.
DB15 (MSB)
DB0 (LSB)
INT
/EXT
X
LDAC
PDB
PBA
A
/B
CR1
CR0
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
|––––––––––––––––––––––––– Control Bits –––––––––––––––––––––––––|––––––––––––––––––––––––– Data Bits –––––––––––––––––––––––––|
Figure 24. Input Shift Register Contents
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