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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | AD7277BRMZ |
| 寤犲晢锛� | Analog Devices Inc |
| 鏂囦欢闋佹暩(sh霉)锛� | 3/29闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC ADC 10BIT 3MSPS HS LP 8MSOP |
| 妯�(bi膩o)婧栧寘瑁濓細 | 50 |
| 浣嶆暩(sh霉)锛� | 10 |
| 閲囨ǎ鐜囷紙姣忕锛夛細 | 3M |
| 鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� | DSP锛孧ICROWIRE?锛孮SPI?锛屼覆琛岋紝SPI? |
| 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 | 1 |
| 鍔熺巼鑰楁暎锛堟渶澶э級锛� | 19.8mW |
| 闆诲闆绘簮锛� | 鍠浕婧� |
| 宸ヤ綔婧害锛� | -40°C ~ 125°C |
| 瀹夎椤炲瀷锛� | 琛ㄩ潰璨艰 |
| 灏佽/澶栨锛� | 8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級 |
| 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 | 8-MSOP |
| 鍖呰锛� | 绠′欢 |
| 杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� | 1 鍊嬪柈绔�锛屽柈妤� |
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AD7276/AD7277/AD7278
Rev. C | Page 10 of 28
TIMING EXAMPLES
For the AD7276, if CS is brought high during the 14
th SCLK rising
edge after the two leading zeros and 12 bits of the conversion
have been provided, the part can achieve the fastest throughput
rate, 3 MSPS. If CS is brought high during the 16
th SCLK rising
edge after the two leading zeros and 12 bits of the conversion
and two trailing zeros have been provided, a throughput rate of
2.97 MSPS is achievable. This is illustrated in the following two
timing examples.
Timing Example 1
throughput is 3 MSPS. This produces a cycle time of t2 +
12.5(1/fSCLK) + tACQ = 333 ns, where t2 = 6 ns minimum and
tACQ = 67 ns.
shows that tACQ comprises 0.5(1/fSCLK) + t8 + tQUIET, where
t8 = 14 ns max. This allows a value of 43 ns for tQUIET, satisfying
the minimum requirement of 4 ns.
Timing Example 2
and the throughput is 2.97 MSPS. This produces a cycle time of
t2 + 12.5(1/fSCLK) + tACQ = 336 ns, where t2 = 6 ns minimum and
tQUIET, where t8 = 14 ns max. This satisfies the minimum
requirement of 4 ns for tQUIET.
04
90
3-
0
05
1
2
34
5
1314
15
16
SCLK
SDATA
THREE-STATE
THREE-
STATE
2 LEADING
ZEROS
2 TRAILING
ZEROS
B
CS
t3
tCONVERT
t2
ZERO
Z
DB11
DB10
DB9
DB1
DB0
ZERO
t6
t5
t8
t1
tQUIET
1/THROUGHPUT
t4
t7
Figure 5. AD7276 Serial Interface Timing Diagram
04
90
3-
0
34
tQUIET
tCONVERT
1/THROUGHPUT
CS
15
13
t4
234
t5
t3
t2
t6
t7
t9
14
B
t1
SCLK
SDATA
THREE-STATE
THREE-
STATE
2 LEADING
ZEROS
ZZERO
DB11
DB10
DB9
DB1
DB0
Figure 6. AD7276 Serial Interface Timing 14 SCLK Cycle
04
90
3-
00
6
123
4
5
13
12
14
15
16
SCLK
B
CS
tCONVERT
t2
t8
t1
tQUIET
1/THROUGHPUT
12.5(1/fSCLK)
tACQUISITION
Figure 7. AD7276 Serial Interface Timing 16 SCLK Cycle
鐩搁棞(gu膩n)PDF璩囨枡 |
PDF鎻忚堪 |
|---|---|
| GTC06A-14S-7S | CONN PLUG 3POS STRAIGHT W/SCKT |
| VE-221-MX-F3 | CONVERTER MOD DC/DC 12V 75W |
| TA8MLX | CONN PLUG CORD MINI 8POS MALE |
| VI-BNV-MW-S | CONVERTER MOD DC/DC 5.8V 100W |
| VI-24W-IU-S | CONVERTER MOD DC/DC 5.5V 200W |
鐩搁棞(gu膩n)浠ｇ悊鍟�/鎶€琛�(sh霉)鍙冩暩(sh霉) |
鍙冩暩(sh霉)鎻忚堪 |
|---|---|
| AD7277BRMZ-REEL | 鍔熻兘鎻忚堪:IC ADC 10BIT 3MSPS HS LP 8MSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 妯�(bi膩o)婧栧寘瑁�:1,000 绯诲垪:- 浣嶆暩(sh霉):16 閲囨ǎ鐜囷紙姣忕锛�:45k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:2 鍔熺巼鑰楁暎锛堟渶澶э級:315mW 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-SOIC W 鍖呰:甯跺嵎 (TR) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:2 鍊嬪柈绔�锛屽柈妤� |
| AD7277BUJ-REEL | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT |
| AD7277BUJZ-500RL7 | 鍔熻兘鎻忚堪:IC ADC 10BIT 3MSPS TSOT23-6 RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 妯�(bi膩o)婧栧寘瑁�:1 绯诲垪:microPOWER™ 浣嶆暩(sh霉):8 閲囨ǎ鐜囷紙姣忕锛�:1M 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶锛孲PI? 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:1 鍔熺巼鑰楁暎锛堟渶澶э級:- 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 宸ヤ綔婧害:-40°C ~ 125°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:24-VFQFN 瑁搁湶鐒婄洡 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:24-VQFN 瑁搁湶鐒婄洡锛�4x4锛� 鍖呰:Digi-Reel® 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:8 鍊嬪柈绔�锛屽柈妤� 鐢�(ch菐n)鍝佺洰閷勯爜闈�:892 (CN2011-ZH PDF) 鍏跺畠鍚嶇ū:296-25851-6 |
| AD7277BUJZ-REEL7 | 鍔熻兘鎻忚堪:IC ADC 10BIT 3MSPS TSOT23-6 RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 妯�(bi膩o)婧栧寘瑁�:1,000 绯诲垪:- 浣嶆暩(sh霉):16 閲囨ǎ鐜囷紙姣忕锛�:45k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:2 鍔熺巼鑰楁暎锛堟渶澶э級:315mW 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-SOIC W 鍖呰:甯跺嵎 (TR) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:2 鍊嬪柈绔�锛屽柈妤� |
| AD7278 | 鍒堕€犲晢:AD 鍒堕€犲晢鍏ㄧū:Analog Devices 鍔熻兘鎻忚堪:3MSPS,12-/10-/8-Bit ADCs in 6-Lead TSOT |
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