VDD = 2.35 V to 3.6 V," />
鍙冩暩(sh霉)璩囨枡
鍨嬭櫉(h脿o)锛� AD7277BRMZ
寤犲晢锛� Analog Devices Inc
鏂囦欢闋�(y猫)鏁�(sh霉)锛� 28/29闋�(y猫)
鏂囦欢澶�?銆�?/td> 0K
鎻忚堪锛� IC ADC 10BIT 3MSPS HS LP 8MSOP
妯�(bi膩o)婧�(zh菙n)鍖呰锛� 50
浣嶆暩(sh霉)锛� 10
閲囨ǎ鐜囷紙姣忕锛夛細 3M
鏁�(sh霉)鎿�(j霉)鎺ュ彛锛� DSP锛孧ICROWIRE?锛孮SPI?锛屼覆琛�锛孲PI?
杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩細 1
鍔熺巼鑰楁暎锛堟渶澶э級锛� 19.8mW
闆诲闆绘簮锛� 鍠浕婧�
宸ヤ綔婧害锛� -40°C ~ 125°C
瀹夎椤炲瀷锛� 琛ㄩ潰璨艰
灏佽/澶栨锛� 8-TSSOP锛�8-MSOP锛�0.118"锛�3.00mm 瀵級
渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁濓細 8-MSOP
鍖呰锛� 绠′欢
杓稿叆鏁�(sh霉)鐩拰椤炲瀷锛� 1 鍊�(g猫)鍠锛屽柈妤�
AD7276/AD7277/AD7278
Rev. C | Page 7 of 28
AD7278 SPECIFICATIONS
VDD = 2.35 V to 3.6 V, fSCLK = 48 MHz, fSAMPLE = 3 MSPS, TA = TMIN to TMAX, unless otherwise noted.
Table 4.
Parameter
B Grade1, 2
Unit
Test Conditions/Comments
DYNAMIC PERFORMANCE
fIN = 1 MHz sine wave
Signal-to-Noise + Distortion (SINAD)3
49
dB min
Total Harmonic Distortion (THD)3
66
67
dB max
73
dB typ
Peak Harmonic or Spurious Noise (SFDR)3
69
dB typ
Intermodulation Distortion (IMD)3
Second-Order Terms
76
dB typ
fa = 1 MHz, fb = 0.97 MHz
Third-Order Terms
76
dB typ
fa = 1 MHz, fb = 0.97 MHz
Aperture Delay
5
ns typ
Aperture Jitter
18
ps typ
Full Power Bandwidth
74
MHz typ
@ 3 dB
Full Power Bandwidth
10
MHz typ
@ 0.1 dB
DC ACCURACY
Resolution
8
Bits
Integral Nonlinearity3
卤0.2
LSB max
Differential Nonlinearity3
卤0.3
LSB max
Guaranteed no missed codes to 8 bits
Offset Error3
卤0.9
卤0.5
LSB max
Gain Error3
卤1.2
卤1
LSB max
Total Unadjusted Error (TUE)3
卤1.5
LSB max
ANALOG INPUT
Input Voltage Ranges
0 to VDD
V
DC Leakage Current
卤1
渭A max
40掳C to +85掳C
卤5.5
渭A max
85掳C to 125掳C
Input Capacitance
42
pF typ
When in track
10
pF typ
When in hold
LOGIC INPUTS
Input High Voltage, VINH
1.7
V min
2.35 V 鈮� VDD 鈮� 2.7 V
2
V min
2.7 V < VDD 鈮� 3.6 V
Input Low Voltage, VINL
0.7
V max
2.35 V 鈮� VDD 鈮� 2.7 V
0.8
V max
2.7 V < VDD 鈮� 3.6 V
Input Current, IIN
卤1
渭A max
Input Capacitance, CIN4
2
pF typ
LOGIC OUTPUTS
Output High Voltage, VOH
VDD 0.2
V min
ISOURCE = 200 渭A, VDD = 2.35 V to 3.6 V
Output Low Voltage, VOL
0.2
V max
ISINK = 200 渭A
Floating-State Leakage Current
卤2.5
渭A max
Floating-State Output Capacitance4
4.5
pF typ
Output Coding
Straight (natural) binary
CONVERSION RATE
Conversion Time
208
ns max
10 SCLK cycles with SCLK at 48 MHz
Track-and-Hold Acquisition Time3
60
ns min
Throughput Rate
4
MSPS max
SCLK at 48 MHz
鐩搁棞(gu膩n)PDF璩囨枡
PDF鎻忚堪
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鍙冩暩(sh霉)鎻忚堪
AD7277BRMZ-REEL 鍔熻兘鎻忚堪:IC ADC 10BIT 3MSPS HS LP 8MSOP RoHS:鏄� 椤炲垾:闆嗘垚闆昏矾 (IC) >> 鏁�(sh霉)鎿�(j霉)閲囬泦 - 妯℃暩(sh霉)杞�(zhu菐n)鎻涘櫒 绯诲垪:- 妯�(bi膩o)婧�(zh菙n)鍖呰:1,000 绯诲垪:- 浣嶆暩(sh霉):16 閲囨ǎ鐜囷紙姣忕锛�:45k 鏁�(sh霉)鎿�(j霉)鎺ュ彛:涓茶 杞�(zhu菐n)鎻涘櫒鏁�(sh霉)鐩�:2 鍔熺巼鑰楁暎锛堟渶澶э級:315mW 闆诲闆绘簮:妯℃摤鍜屾暩(sh霉)瀛� 宸ヤ綔婧害:0°C ~ 70°C 瀹夎椤炲瀷:琛ㄩ潰璨艰 灏佽/澶栨:28-SOIC锛�0.295"锛�7.50mm 瀵級 渚涙噳(y墨ng)鍟嗚ō(sh猫)鍌欏皝瑁�:28-SOIC W 鍖呰:甯跺嵎 (TR) 杓稿叆鏁�(sh霉)鐩拰椤炲瀷:2 鍊�(g猫)鍠锛屽柈妤�
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