參數(shù)資料
型號(hào)： AD7266BSUZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 11/29頁(yè)
文件大?。?/td> 0K
描述： IC ADC 12BIT 3CH 2MSPS 32-TQFP
設(shè)計(jì)資源： AD7266 SAR ADC in DC-Coupled Differential and Single-Ended Appls (CN0039)
標(biāo)準(zhǔn)包裝： 1
位數(shù)： 12
采樣率（每秒）： 2M
數(shù)據(jù)接口： DSP，MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 2
功率耗散（最大）： 33.6mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 125°C
安裝類型： 表面貼裝
封裝/外殼： 32-TQFP
供應(yīng)商設(shè)備封裝： 32-TQFP（7x7）
包裝： 托盤(pán)
輸入數(shù)目和類型： 12 個(gè)單端，單極；6 個(gè)差分，單極；6 個(gè)偽差分，單極
產(chǎn)品目錄頁(yè)面： 777 (CN2011-ZH PDF)
AD7266
Rev. B | Page 18 of 28
TRANSFER FUNCTIONS
The designed code transitions occur at successive integer LSB
values (1 LSB, 2 LSB, and so on). In single-ended mode, the LSB
size is VREF/4096 when the 0 V to VREF range is used, and the
LSB size is 2 × VREF/4096 when the 0 V to 2 × VREF range is used.
In differential mode, the LSB size is 2 × VREF /4096 when the 0 V
to VREF range is used, and the LSB size is 4 × VREF/4096 when the
0 V to 2 × VREF range is used. The ideal transfer characteristic
for the AD7266 when straight binary coding is output is shown
in Figure 32, and the ideal transfer characteristic for the
AD7266 when twos complement coding is output is shown in
Figure 33 (this is shown with the 2 × VREF range).
04603-027
000...000
111...111
1LSB = VREF/4096
1LSB
VREF – 1LSB
ANALOG INPUT
ADC
CODE
0V
000...001
000...010
111...110
111...000
011...111
NOTE
1. VREF IS EITHER VREF OR 2 × VREF.
Figure 32. Straight Binary Transfer Characteristic
04603-028
100...000
011...111
1LSB = 2
× VREF/4096
+VREF – 1 LSB
–VREF + 1LSB VREF – 1LSB
ANALOG INPUT
ADC
CODE
100...001
100...010
011...110
000...001
000...000
111...111
Figure 33. Twos Complement Transfer Characteristic with
VREF ± VREF Input Range
DIGITAL INPUTS
The digital inputs applied to the AD7266 are not limited by the
maximum ratings that limit the analog inputs. Instead, the
digital inputs can be applied up to 7 V and are not restricted by
the VDD + 0.3 V limit as are the analog inputs. See the Absolute
Maximum Ratings section for more information. Another
advantage of the SCLK, RANGE, A0 to A2, and CS pins not
being restricted by the VDD + 0.3 V limit is that power supply
sequencing issues are avoided. If one of these digital inputs is
applied before VDD, there is no risk of latch-up, as there would
be on the analog inputs if a signal greater than 0.3 V were
applied prior to VDD.
VDRIVE
The AD7266 also has a VDRIVE feature to control the voltage at
which the serial interface operates. VDRIVE allows the ADC to
easily interface to both 3 V and 5 V processors. For example, if
the AD7266 was operated with a VDD of 5 V, the VDRIVE pin
could be powered from a 3 V supply, allowing a large dynamic
range with low voltage digital processors. Therefore, the
AD7266 could be used with the 2 × VREF input range, with a VDD
of 5 V while still being able to interface to 3 V digital parts.
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