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參數(shù)資料
| 型號(hào)： | AD7191BRUZ |
| 廠(chǎng)商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 7/21頁(yè) |
| 文件大小： | 0K |
| 描述： | IC ADC 2CH 24B SD 24TSSOP |
| 產(chǎn)品培訓(xùn)模塊： | Weigh Scale Introduction |
| 設(shè)計(jì)資源： | Precision Weigh Scale Design Using AD7191 with Internal PGA (CN0118) |
| 標(biāo)準(zhǔn)包裝： | 62 |
| 位數(shù)： | 24 |
| 采樣率（每秒）： | 120 |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 105°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 24-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 24-TSSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類(lèi)型： | 2 個(gè)差分，雙極 |
| 產(chǎn)品目錄頁(yè)面： | 777 (CN2011-ZH PDF) |
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AD7191
Rev. A | Page 14 of 20
ADC CIRCUIT INFORMATION
OVERVIEW
The AD7191 is a low noise, complete analog front end for high
precision measurement applications. It contains a low noise,
24-bit, Σ-Δ ADC, a PGA, and an on-chip digital filter intended
for measuring wide dynamic range signals.
The device has an internal clock and two differential analog
inputs. It offers a choice of four output data rates (10 Hz, 50 Hz,
60 Hz, and 120 Hz) and four gain settings (1, 8, 64, and 128).
The device also has an internal temperature sensor. These
functions are controlled using dedicated pins, which make the
interface easy to configure. A 2-wire interface simplifies data
retrieval from the AD7191.
FILTER, DATA RATE, AND SETTLING TIME
The AD7191 has four output data rates, which are selected
using the ODR2 and ODR1 pins (see Table 5). When the
polarity of ODR2 or ODR1 is changed, the AD7191 modulator
and filter are reset immediately. DOUT/RDY is set high, and
the ADC then begins conversions using the selected output data
rate. The first conversion requires the complete settling time of
the filter. Subsequent conversions occur at the selected output
data rate. The settling time of the digital filter, tSETTLE, is
tSETTLE = 4/Output Data Rate
That is, the settling time is equal to four conversion cycles.
When a step change occurs on the analog input, the AD7191
requires several conversion cycles to generate a valid conversion.
If the step change occurs synchronous to the conversion period
(see Figure 17), then to generate a valid conversion, the settling
time of the AD7191 must be allowed. If the step change occurs
asynchronous to the end of a conversion (see Figure 18), then to
generate a valid conversion, an extra conversion period must be
allowed. The diagrams show the case for an output data rate of
50 Hz; therefore, an asynchronous step change can increase the
time to generate a valid conversion by 20 ms. The data register
is updated with all the conversions but, for an accurate result,
the user must allow the required time.
ANALOG INPUT
ADC OUTPUT
0ms
20ms
40ms
60ms
80ms
100ms
VALID
08
16
3-
0
11
Figure 17. Synchronous Analog Input Step Change
ANALOG INPUT
ADC OUTPUT
VALID
0ms
20ms
40ms
60ms
80ms
100ms
120ms
08
16
3-
01
2
Figure 18. Asynchronous Analog Input Step Change
allowed output data rates. The filter provides more than 53 dB
of rejection in the stop band. When the output data rate is equal
to 10 Hz, 60 Hz, or 120 Hz, the first notch occurs at a frequency
equal to the output data rate. The other notches occur at multiples
of the output data rate. Therefore, when the output data rate is
equal to 10 Hz, notches are placed at 50 Hz and 60 Hz, giving
simultaneous 50 Hz/60 Hz rejection. When the 60 Hz output
data rate is selected, 60 Hz rejection is achieved. When the
50 Hz output data rate is selected, notches are placed at 50 Hz
and multiples of 50 Hz. A notch is also placed at 60 Hz. This
gives simultaneous 50 Hz/60 Hz rejection for an output data
rate of 50 Hz.
When the output data rate is changed, DOUT/RDY goes high
and remains high until the appropriate settling time has elapsed.
Therefore, the user should complete any read operations before
changing the output data rate. Otherwise, 1s are read back from
the AD7191 as the DOUT/RDY pin is set high following the
change in output data rate.
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
10
2030
4050
607080
90
100
FREQUENCY (Hz)
FI
LT
E
R
G
A
IN
(d
B
)
08
16
3-
0
13
Figure 19. Filter Profile for the 10 Hz Output Data Rate
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
30
60
90
120
150
180
210
240
FREQUENCY (Hz)
FI
LT
E
R
G
A
IN
(d
B
)
08
16
3-
0
14
Figure 20. Filter Profile for the 50 Hz Output Data Rate
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7191BRUZ | 制造商:Analog Devices 功能描述:IC ADC 24BIT 120SPS TSSOP-24 |
| AD7191BRUZ-REEL | 功能描述:IC ADC 24BIT 2CH LN SD 24TSSOP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):16 采樣率（每秒）:45k 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 功率耗散（最大）:315mW 電壓電源:模擬和數(shù)字 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:28-SOIC W 包裝:帶卷 (TR) 輸入數(shù)目和類(lèi)型:2 個(gè)單端，單極 |
| AD7191KSTZ | 制造商:Analog Devices 功能描述: |
| AD7191S/0B | 制造商:Sony Nec Optiarc America 功能描述:DOUBLE DUAL INTERNAL DVDRW SATA BEZEL 20X/18X12XRAM - Bulk |
| AD7192 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:4.8 kHz, Ultralow Noise, 24-Bit Sigma-Delta ADC with PGA |
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