參數(shù)資料
型號(hào)： AD7191BRUZ-REEL
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 8/21頁(yè)
文件大小： 0K
描述： IC ADC 24BIT 2CH LN SD 24TSSOP
設(shè)計(jì)資源： Precision Weigh Scale Design Using AD7191 with Internal PGA (CN0118)
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 24
采樣率（每秒）： 120
數(shù)據(jù)接口： MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 105°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 2 個(gè)差分，雙極
AD7191
Rev. A | Page 15 of 20
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
30
60
90
120
150
180
210
240
FREQUENCY (Hz)
FI
LT
E
R
G
A
IN
(d
B
)
08
16
3-
0
15
Figure 21. Filter Profile for the 60 Hz Output Data Rate
–120
–110
–100
–90
–80
–70
–60
–50
–40
–30
–20
–10
0
30
60
90
120
150
180
210
240
FREQUENCY (Hz)
FI
LT
E
R
G
A
IN
(d
B
)
08
16
3-
0
16
Figure 22. Filter Profile for the 120 Hz Output Data Rate
GAIN
The AD7191 has four gain options: gain = 1, gain = 8, gain = 64,
and gain = 128. The PGA2 and PGA1 pins are used to set the
gain. The analog input range is +VREF/gain. Table 7 shows the
gains and the corresponding analog input ranges.
Table 7. Gain Settings
PGA2
PGA1
GAIN
Input Range
0
1
±VREF
0
1
8
±VREF/8
1
0
64
±VREF/64
1
128
±VREF/128
When the polarity of the PGA2 pin or PGA1 pin is changed,
the AD7191 modulator and filter are reset immediately. DOUT/
RDY is set high. The ADC then begins conversions. DOUT/
RDY remains high until the appropriate settling time for the
filter has elapsed. Therefore, any read operations should be
completed before changing the gain. Otherwise, all 1s are read
back from the AD7191 as the DOUT/RDY pin is set high
following the gain change. The complete settling time of the
filter is required to generate the first conversion after the gain
change, whereas subsequent conversions occur at the selected
output data rate.
ANALOG INPUT CHANNELS
The AD7191 has two differential analog input channels, AIN1/
AIN2 and AIN3/AIN4. Each input channel feeds into a high
impedance input stage of the amplifier. Therefore, the input
can tolerate high source impedances and is tailored for direct
connection to external resistive-type sensors such as strain
gauges or loadcells. The channel is selected using the CHAN
pin. When CHAN is tied low, channel AIN1/AIN2 is selected,
whereas channel AIN3/AIN4 is selected when the CHAN pin
is tied high.
The absolute input voltage range is restricted to a range between
AGND + 250 mV and AVDD 250 mV. Care must be taken in
setting up the common-mode voltage to avoid exceeding these
limits. Otherwise, there is degradation in linearity and noise
performance.
The low noise PGA means that signals of small amplitude can
be amplified within the AD7191 while still maintaining excel-
lent noise performance. The amplifier can be configured to have
a gain of 1, 8, 64, or 128 using the PGA2 and PGA1 pins. The
analog input range is equal to ±VREF/gain.
The analog input range must be limited to (AVDD – 1.25 V)/gain
because the PGA requires some headroom. Therefore, if AVDD =
5 V, the maximum analog input that can be applied to the
AD7191 is ±3.75 V/gain.
When the channel is changed, DOUT/RDY goes high and
remains high until the appropriate settling time has elapsed.
Therefore, any read operations should be completed before
changing the channel. Otherwise, all 1s are read back from the
AD7191 as the DOUT/RDY pin is set high following the
channel change.
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